Cypress Semiconductor CY7C1440AV33 Specification Sheet Download | Manualshive

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36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined Sync SRAM

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document #: 38-05383 Rev. *E

Revised June 23, 2006

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V/3.3V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

•

User-selectable burst counter supporting Intel

®

Pentium

®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• CY7C1440AV33, CY7C1442AV33 available in lead-free

100-pin TQFP package, lead-free and non-lead-free
165-ball FBGA package. CY7C1446AV33 available in
lead-free and non-lead-free 209-ball FBGA package

• Also available in lead-free packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Functional Description

[1]

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM
integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

1

), depth-expansion Chip Enables (CE

2

and

CE

3

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables (BW

X

and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

167 MHz

Unit

Maximum Access Time

2.6

3.2

3.4

ns

Maximum Operating Current

475

425

375

mA

Maximum CMOS Standby Current

120

120

120

mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

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Summary of Contents for CY7C1440AV33

Page 1: ...ronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE1 depth expansion Chip Enables CE2 and CE3 Burst Control inputs ADSC ADSP and ADV Write Enables BWX and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin Addresses and chip en...

Page 2: ...WRITE REGISTER DQB DQPB BYTE WRITE REGISTER DQC DQPC BYTE WRITE REGISTER DQD DQPD BYTE WRITE REGISTER DQA DQPA BYTE WRITE DRIVER DQB DQPB BYTE WRITE DRIVER DQC DQPC BYTE WRITE DRIVER DQD DQPD BYTE WRITE DRIVER A0 A1 A ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSC BWB BWA CE1 DQB DQPB WRITE REGISTER DQA DQPA WRITE REGISTER ENABLE REGISTER OE SENSE AMPS MEMORY ARRAY ADSP 2 MODE CE2...

Page 3: ...ERS MEMORY ARRAY OUTPUT BUFFERS E DQA DQPA WRITE DRIVER DQB DQPB WRITE DRIVER DQC DQPC WRITE DRIVER DQD DQPD WRITE DRIVER INPUT REGISTERS BYTE a WRITE DRIVER DQE DQPE WRITE DRIVER DQF DQPF WRITE DRIVER DQG DQPG WRITE DRIVER DQH DQPH WRITE DRIVER SENSE AMPS SLEEP CONTROL ZZ DQA DQPA WRITE DRIVER DQB DQPB WRITE DRIVER DQC DQPC WRITE DRIVER DQD DQPD WRITE DRIVER DQE DQPE WRITE DRIVER DQF DQPF WRITE D...

Page 4: ... 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1440AV33 1M x 36 NC A A A A A 1 A 0 NC 72M A V SS V DD A A A A A A A A A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW ...

Page 5: ...DQB DQB DQB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A CY7C1442AV33 2M x 18 A0 A VSS 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 288M NC 144M NC NC DQPB NC DQB A CE1 NC CE3 BWB BWE A CE2 NC DQB DQB MODE NC DQB DQB NC NC NC A NC 72M VDDQ NC BWA CLK GW VSS VSS VSS VSS VDDQ VSS V...

Page 6: ...VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ Pin Definitions Name I O Description A0 A1 A Input Synchronous Address Inputs used to select one of the address locations Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW and CE1 CE2 and CE3 2 are sampled active A1 A0 are fed to the two bit counter BWA BWB BWC BWD BWE BWF BWG BWH Input Synchronous Byte Write Select Inputs active LOW Qualified with B...

Page 7: ...t floating ZZ pin has an internal pull down DQs DQPX I O Synchronous Bidirectional Data I O lines As inputs they feed into an on chip data register that is triggered by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is...

Page 8: ... rise the data presented to the DQs inputs is written into the corre sponding address location in the memory array If GW is HIGH then the Write operation is controlled by BWE and BWX signals The CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 provides Byte Write capability that is described in the Write Cycle Descriptions table Asserting the Byte Write Enable input BWE with the selected Byte Write BWX inpu...

Page 9: ... Burst External L H L L H L X L X L H D READ Cycle Begin Burst External L H L L H L X H L L H Q READ Cycle Begin Burst External L H L L H L X H H L H Tri State READ Cycle Continue Burst Next X X X L H H L H L L H Q READ Cycle Continue Burst Next X X X L H H L H H L H Tri State READ Cycle Continue Burst Next H X X L X H L H L L H Q READ Cycle Continue Burst Next H X X L X H L H H L H Tri State WRIT...

Page 10: ... L H L H L Write Bytes C B H L H L L H Write Bytes C B A H L H L L L Write Byte D DQD and DQPD H L L H H H Write Bytes D A H L L H H L Write Bytes D B H L L H L H Write Bytes D B A H L L H L L Write Bytes D C H L L L H H Write Bytes D C A H L L L H L Write Bytes D C B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read Write 4 8 9 Function CY7C1442AV33 GW BWE B...

Page 11: ...g edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction regi...

Page 12: ...are possible with the three bit instruction register All combinations are listed in the Instruction Codes table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state ins...

Page 13: ... 165 FBGA package or bit 138 for 209 FBGA package When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it will directly control the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it will enable the output buffers to drive the output bus When LOW this bit will ...

Page 14: ... time requirements of latching data from the boundary scan register 11 Test conditions are specified using the load in TAP AC test Conditions tR tF 1 ns TAP AC Switching Characteristics Over the operating Range 10 11 Parameter Description Min Max Unit Clock tTCYC TCK Clock Cycle Time 50 ns tTF TCK Clock Frequency 20 MHz tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns Output Times tTDOV ...

Page 15: ...rnal Use Architecture Memory Type 23 18 000000 000000 000000 Defines memory type and architecture Bus Width Density 17 12 100111 010111 110111 Defines width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 1 Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size x...

Page 16: ...Codes continued Instruction Code Description 165 ball FBGA Boundary Scan Order 14 15 CY7C1440AV33 1M x 36 CY7C1442AV33 2M x 18 Bit ball ID Bit ball ID Bit ball ID Bit ball ID 1 N6 26 E11 51 A3 76 N1 2 N7 27 D11 52 A2 77 N2 3 N10 28 G10 53 B2 78 P1 4 P11 29 F10 54 C2 79 R1 5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 P3 7 R9 32 C11 57 C1 82 R3 8 P9 33 A11 58 D1 83 P2 9 P10 34 B11 59 E1 84 R4 10 R10...

Page 17: ...N1 11 V9 46 F11 81 A4 116 P2 12 U9 47 F10 82 B4 117 P1 13 P6 48 E10 83 C3 118 R2 14 W11 49 E11 84 B3 119 R1 15 W10 50 D11 85 A3 120 T2 16 V11 51 D10 86 A2 121 T1 17 V10 52 C11 87 A1 122 U2 18 U11 53 C10 88 B2 123 U1 19 U10 54 B11 89 B1 124 V2 20 T11 55 B10 90 C2 125 V1 21 T10 56 A11 91 C1 126 W2 22 R11 57 A10 92 D2 127 W1 23 R10 58 C9 93 D1 128 T6 24 P11 59 B9 94 E1 129 U3 25 P10 60 A9 95 E2 130 V...

Page 18: ...0 mA 0 4 V for 2 5V I O IOL 1 0 mA 0 4 V VIH Input HIGH Voltage 17 for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 17 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ ...

Page 19: ...ance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 25 21 20 8 25 31 C W ΘJC Thermal Resistance Junction to Case 2 28 3 2 4 48 C W AC Test Loads and Waveforms Note 19 Tested initially and after any design or process change that may affect these parameters OUTPUT R 317Ω R 351Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL ...

Page 20: ...Hold Times tAH Address Hold After CLK Rise 0 3 0 4 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 3 0 4 0 5 ns tADVH ADV Hold After CLK Rise 0 3 0 4 0 5 ns tWEH GW BWE BWX Hold After CLK Rise 0 3 0 4 0 5 ns tDH Data Input Hold After CLK Rise 0 3 0 4 0 5 ns tCEH Chip Enable Hold After CLK Rise 0 3 0 4 0 5 ns Notes 20 This part has a voltage regulator internally tPOWER is the time that the power needs ...

Page 21: ... or CE2 is LOW or CE3 is HIGH tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW BWE BWx Data Out Q High Z tCLZ tDOH tCO ADV tOEHZ tCO Single READ BURST READ tOEV tOELZ tCHZ ADV suspends burst Burst wraps around to its initial state tADVH tADVS tWEH tWES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A2 3 A2 A3 Deselect cycle Burst continued with new base address DON T...

Page 22: ...CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE BWX Data Out Q High Z ADV BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Data In D Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ t ADVH t ADVS tWEH tWES tDH tDS GW tWEH tWES Byte write signals are ignored for first cycle when ADSP initiates burst ADSC extends burst ADV suspends ...

Page 23: ...access is initiated by ADSP or ADSC 29 GW is HIGH Switching Waveforms continued tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES BWE BWX Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6 Data In D BURST READ Back to Back READs High Z Q A2 Q A1 Q A4 Q A4 1 Q A4 2 tWEH tWES Q A4 3 tOEHZ tDH tDS tOELZ tCLZ tCO Back to Back WRITEs A1 DON T CARE UNDEFINED A3 Feedback ...

Page 24: ...eselected when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 31 DQs are in high Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI tRZZI Outputs Q High Z DESELECT or READ Only Feedback ...

Page 25: ...40AV33 167BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1442AV33 167BZXI CY7C1446AV33 167BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C1446AV33 167BGXI 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm Lead Free 200 CY7C1440AV33 200AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1442AV33 200AXC CY7C1440AV33 ...

Page 26: ...CY7C1440AV33 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1442AV33 250AXI CY7C1440AV33 250BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1442AV33 250BZI CY7C1440AV33 250BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1442AV33 250BZXI CY7C1446AV33 250BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 2...

Page 27: ...R SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 31 50 51 80 81 GAUGE PLANE 1 00 REF 0 20 MIN SEATING PLANE 100 p...

Page 28: ...0 1 00 Ø0 45 0 05 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A C 1 00 5 00 0 36 0 05 0 10 165 ball FBGA 15 x 17 x 1 4 mm 51 85165 51 85165 A Feedback ...

Page 29: ...express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemni...

Page 30: ...on for 100 pin TQFP 165 FBGA and 209 FBGA Packages Changed IDD from 450 400 and 350 mA to 475 425 and 375 mA for frequencies of 250 200 and 167 MHz respectively Changed ISB1 from 190 180 and 170 mA to 225 mA for frequencies of 250 200 and 167 MHz respectively Changed ISB2 from 80 to 100 mA Changed ISB3 from 180 170 and 160 mA to 200 mA for frequencies of 250 200 and 167 MHz respectively Changed IS...

Page 31: ...ive to GND Changed tTH tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table Document Title CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36 Mbit 1M x 36 2M x 18 512K x 72 Pipelined Sync SRAM Document Number 38 05383 REV ECN NO Issue Date Orig of Change Description of Change Feedback ...

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