ARM AMBA NIC-301 Technical Reference Manual Download

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ARM DDI 0397G (ID031010)

AMBA

Network Interconnect (NIC-301)

Revision: r2p1

Technical Reference Manual

Summary of Contents for AMBA NIC-301

Page 2: ...ist the reader in the use of the product ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Where the term ARM is used it means ARM or any of its subsidiaries as appropriate Confidentiality Status This document is Non Confidential The right to use copy and disclose ...

Page 3: ...Introduction 1 1 About the AMBA Network Interconnect 1 2 1 2 Key features 1 3 1 3 Relationship between AMBA Network Interconnect and AMBA Designer 1 4 1 4 Product revisions 1 5 Chapter 2 Functional Description 2 1 About the functions 2 2 2 2 Interfaces 2 3 2 3 Operation 2 12 Chapter 3 Programmers Model 3 1 About this programmers model 3 2 3 2 Configuration programmers model 3 3 Appendix A Revision...

Page 4: ...tion 2 13 Table 2 4 Conversion of WRAP bursts by the upsize function 2 13 Table 2 5 Conversion of INCR bursts by the downsize function 2 14 Table 2 6 Conversion of FIXED bursts by the downsize function 2 15 Table 2 7 How to change modes 2 16 Table 3 1 Registers for each ASIB 3 4 Table 3 2 Registers for each IB 3 5 Table 3 3 Registers for each AMIB 3 6 Table 3 4 Address region control registers 3 7...

Page 5: ...t NIC 301 Technical Reference Manual Figure 1 1 AMBA Network Interconnect top level block diagram 1 2 Figure 2 1 No remap remap set to 000 2 22 Figure 2 2 Remap set to 001 2 22 Figure 2 3 Remap set to 010 2 22 Figure 2 4 Remap set to 011 2 23 Figure 2 5 Remap set to 101 2 23 Figure 3 1 Address map of the programmers model 3 3 ...

Page 6: ...ight 2006 2010 ARM All rights reserved vi ID031010 Non Confidential Preface This preface introduces the AMBA Network Interconnect NIC 301 It contains the following sections About this book on page vii Feedback on page ix ...

Page 7: ...apter 2 Functional Description Read this for a description of the major interfaces and components of the AMBA Network Interconnect The chapter also describes how they operate Chapter 3 Programmers Model Read this for a description the address map and registers of the AMBA Network Interconnect Appendix A Revisions Read this for a description of the technical changes between released issues of this ...

Page 8: ...rted means HIGH for active HIGH signals LOW for active LOW signals Lower case n At the start or end of a signal name denotes an active LOW signal Additional reading This section lists publications by ARM and by third parties See Infocenter http infocenter arm com for access to ARM documentation ARM publications This book contains information that is specific to this product See the following docum...

Page 9: ...pplier and give The product name The product revision or version An explanation with as much information as you can provide Include symptoms and diagnostic procedures if appropriate Feedback on content If you have comments on content then send an e mail to errata arm com Give the title the number ARM DDI 0397G the page numbers to which your comments apply a concise explanation of your comments ARM...

Page 10: ...hapter 1 Introduction This chapter introduces the AMBA Network Interconnect It contains the following sections About the AMBA Network Interconnect on page 1 2 Key features on page 1 3 Relationship between AMBA Network Interconnect and AMBA Designer on page 1 4 Product revisions on page 1 5 ...

Page 11: ...t AMBA protocols An AMBA Network Interconnect configuration can consist of multiple switches with many topology options Figure 1 1 shows a top level block diagram of the AMBA Network Interconnect that contains multiple switches multiple AMBA Slave Interface Blocks ASIBs multiple AMBA Master Interface Blocks AMIBs Figure 1 1 AMBA Network Interconnect top level block diagram Switch A Switch B Interf...

Page 12: ...ol for FIFO transaction release Multiple switch networks Complex topologies including Network On Chip NOC loop back connections between switches Up to five cascaded switch networks between any master and slave interface pair AXI or AHB Lite masters and slaves with an address width of 32 64 bits a data width of 32 64 128 or 256 bits Non contiguous APB slave address map for a single master interface...

Page 13: ...mation that each documentation suite provides AMBA Network Interconnect documentation AMBA Designer documentation 1 3 1 AMBA Network Interconnect documentation The AMBA Network Interconnect documentation consists of TRM The Technical Reference Manual TRM describes how to create the transfer function and possible capabilities of the network component and how to dynamically change it using the progr...

Page 14: ... a non programmable Round Robin RR scheme You can select and configure arbitration schemes for each master interface The APB programming interface enables you to program and interrogate the new separate arbitration schemes The AHB to AXI bridge is optimized for accessing memory is updated with performance enhancements and to fix a defect The way arbitration schemes are described has changed to ena...

Page 15: ...outstanding downsizer transactions Upsizer packs data into the wide bus instead of an expander for data width changes Global dynamic QoS instead of local static QoS Internally programmable instead of externally programmed System level address map replaces an address map for each interconnect Extended timing closure options replace limited timing closure options 256 bit maximum data width instead o...

Page 16: ...rved 2 1 ID031010 Non Confidential Chapter 2 Functional Description This chapter describes the functionality of the AMBA Network Interconnect It contains the following sections About the functions on page 2 2 Interfaces on page 2 3 Operation on page 2 12 ...

Page 17: ...idth crossing used to create timing isolation for optimizing critical network paths for latency Within a domain a switch or multiple switches can exist to enable routing paths between any slave interface to any master interface The functions are configured into routing switches or Interface Blocks IBs and you can use AMBA Designer to create highly complex topologies using these modules For more in...

Page 18: ...back to an AHB master ERROR if you do not configure the early write response you configure INCR Promotion and Early Write Response and the transaction is non cacheable the AHB burst is not broken AXI slave interfaces An AXI slave interface supports the full AXI protocol Configuration options You can configure the following properties Address width of 32 64 bits Data width of 32 64 128 or 256 bits ...

Page 19: ...ect can support the full AHB Lite protocol using either an AHB Lite slave interface an AHB Lite mirror master interface The following configuration options can improve AHB Lite to AXI performance but cannot always be used robustly INCR promotion and Early Write Response allow broken bursts If you configure the interface as an AHB mirror master interface you cannot configure allow broken bursts bec...

Page 20: ...feed it back to the master Read INCR bursts with HPROT 3 negated to a series of AXI singles Write INCR bursts with HPROT 3 negated to a series of AXI singles and each AHB write beat is acknowledged with the AXI buffered write response Combination 2 If you configure allow broken bursts and do not configure INCR promotion and Early Write Response the network converts all Read fixed length bursts wit...

Page 21: ...eries of AXI singles Write INCR bursts with HPROT 3 negated to a series of AXI singles and each AHB write beat is acknowledged with the AXI buffered write response Combination 4 If you do not configure INCR promotion and Early Write Response and do not configure allow broken bursts then the network converts all read fixed length bursts to AXI fixed length bursts write fixed length bursts to AXI fi...

Page 22: ...eated See Chapter 3 Programmers Model Configuration options You can configure the following AHB options AHB slave or master mirror interface types Address width of 32 64 bits Data width of 32 64 128 or 256 bits Data width upsize function that Upsizing data width function on page 2 12 describes Data width downsize function that Downsizing data width function on page 2 14 describes Frequency domain ...

Page 23: ...its Data width of 32 64 128 or 256 bits Data width upsize function that Upsizing data width function on page 2 12 describes User sideband signal width of 0 32 bits Data width downsize function that Downsizing data width function on page 2 14 describes Frequency domain crossing of type ASYNC SYNC 1 1 SYNC 1 n SYNC n 1 SYNC n m Support for the full AXI protocol Note You can reduce the gate count and...

Page 24: ...count implementation See Chapter 3 Programmers Model The network still transmits the unaligned address transfer into the AHB domain but it aligns the address by forcing the lower address bits of the transaction s size to zeros The network breaks any transactions that cross a 1KB boundary into two AHB INCR bursts You can configure a programmable option named force_incr see Table 3 3 on page 3 6 tha...

Page 25: ...nd non secure transactions to access components attached to this master using the Secure and Non secure options above Support for the full AHB Lite master protocol Timing isolation from the external slave from the network APB master interfaces You can configure the APB interface to support a mixture of APB2 or APB3 The APB data width is always 32 bit and it is therefore never necessary for the APB...

Page 26: ...tion that Downsizing data width function on page 2 14 describes frequency domain crossing for the majority of APB ports of the following types ASYNC SYNC 1 1 SYNC 1 n SYNC n 1 SYNC n m buffering that FIFO and clocking function on page 2 15 describes 1 16 supported APB slaves configurable address region sizes non contiguous address regions you can configure each APB slave for APB2 or APB3 asynchron...

Page 27: ... that the address is aligned to the output data width word boundary after the network aligns it to the size of the transfer an unaligned input burst means that the network does not align the address to the output data width word boundary even after it aligns it to the size of the transfer if a transaction passes through this means that the upsize function does not change the input transaction size...

Page 28: ... the output data width to a single INCR Fixed bursts All FIXED bursts pass through unconverted Bypass merge You can configure the upsizer function to have a programmable bit named bypass_merge If bypass_merge is asserted the network does not alter any transactions that could pass through legally without alteration Table 2 3 Conversion of INCR bursts by the upsize function INCR burst type Converted...

Page 29: ...payload size of the output data bus to a single INCR It converts INCR bursts that are greater than the maximum payload size of the output data bus to multiple INCR bursts Table 2 5 shows how the network converts INCR bursts when it downsizes them INCR bursts with a size that matches the output data width pass through unconverted The AMBA Network Interconnect packs INCR bursts with a SIZE smaller t...

Page 30: ...ta width word boundary even after the network aligns it to the transfer size If a transaction passes through this means that the downsize function does not change the input transaction size and type Note If an exclusive transaction is split into multiple transactions at the output of the downsizer the exclusive flag is removed and the master never receives an EXOKAY response Response priority is t...

Page 31: ...s use a single flop to synchronize each pointer when the ratio is not 1 that is both sides of m n and the slower side of m 1 and n 1 For a 1 1 ratio no extra synchronization is performed on either side Changing the synchronization when you select programmable mode You can change the boundary type by modifying the synchronization that is applied to the two pointers as they pass between domains This...

Page 32: ...ions at an arbitration node with the same QoS that require arbitration then the Network uses a Least Recently Used LRU algorithm 2 3 5 Cyclic Dependency Avoidance Schemes CDAS Because the AXI protocol permits re ordering of transactions it might be necessary for the AMBA Network Interconnect to enforce rules to prevent deadlock when routing multiple transactions concurrently to multiple slaves fro...

Page 33: ...ed The AMBA Designer tool automatically detects when this is required See Additional reading on page viii 2 3 6 Lock support You set support for locked transaction for masters and slaves at configuration time The AMBA Network Interconnect infrastructure is configured for lock support into all switch master interfaces that are required to provide lock support for all the relevant masters and slaves...

Page 34: ...rity checks that are not within the scope of the network are Physical attack Physical attack on the device Non TrustZone aware masters being made secure A master might require access to the Global Programmers View GPV and in this case you can tie the security transaction indicator bits so that all accesses by that master are indicated as secure This places that master permanently in the secure dom...

Page 35: ...ure a dedicated configuration port to gain access to the GPV then you must connect it to a secure master or have a security check that is external to the AMBA Network Interconnect Security checking for master interfaces You can configure each master interface to be Always secure The master rejects non secure transactions Always non secure The master accepts both secure and non secure transactions ...

Page 36: ...te with the lowest remap bit number takes precedence You can configure each slave interface independently so that a remap state can perform different functions for different masters A remap state can alias a memory region into two different address ranges move an address region remove an address region Because of the nature of the distributed register sub system the masters receive the updated rem...

Page 37: ...0 region 0 alias can be removed as Figure 2 2 shows Figure 2 2 Remap set to 001 Alternatively you can move slave 1 to the bottom of the address range by setting remap to 010 as Figure 2 3 shows Figure 2 3 Remap set to 010 Note Remap bit 0 still takes precedence if you set it as Figure 2 4 on page 2 23 shows Slave 0 region 0 Slave 0 region 1 Slave 1 Slave 2 Slave 0 region 0 Slave 3 region 1 Slave 0...

Page 38: ...igure 2 4 Remap set to 011 In addition you can remove memory regions entirely Figure 2 5 shows that if you set remap to 101 Slave 1 is removed Figure 2 5 Remap set to 101 Slave 0 region 0 Slave 0 region 1 Slave 2 Slave 3 region 0 Slave 1 Slave 0 region 0 Slave 0 region 1 Slave 2 Slave 3 region 0 Slave 3 region 1 ...

Page 39: ...ll rights reserved 3 1 ID031010 Non Confidential Chapter 3 Programmers Model This chapter describes the programmers model It contains the following sections About this programmers model on page 3 2 Configuration programmers model on page 3 3 ...

Page 40: ...RM All rights reserved 3 2 ID031010 Non Confidential 3 1 About this programmers model This chapter describes the architecture of the AMBA Network Interconnect AMBA infrastructure component It describes the programmers interface and system characteristics ...

Page 41: ...etwork Interconnect configuration one register block for each IB where the IB can be AXI Slave Interface Block ASIB see Table 3 1 on page 3 4 AXI Master Interface Block AMIB see Table 3 2 on page 3 5 AXI internal network Interface Block IB see Table 3 3 on page 3 6 Figure 3 1 shows the address map of the programmers model It contains one fixed base address and all the other programmers model 4KB b...

Page 42: ...0x008 Reserved 0x00C Reserved 0x020 RW 3 4 sync_mode This register is only present if you configure the block as a programmable FIFO You can configure the register bits as follows 0 sync 1 1 1 sync n 1 2 sync 1 n 3 sync m n 4 async 5 reserved 6 reserved 7 reserved 0x024 RW 1 0 fn_mod2 Bypass merge This register is only present if upsizing or downsizing see Upsizing data width function on page 2 12...

Page 43: ...ss offset Type Width Reset value Name Description 0x000 Reserved 0x004 Reserved 0x008 RW 2 0 fn_mod_bm_iss Bus matrix issuing functionality modification register This register is only present if the block is connected directly to a switch This register sets the issuing capability of the preceding switch arbitration scheme to 1 You can configure the register bits as follows 0 Read issuing read_iss_...

Page 44: ...Address offset Type Width Reset value Name Description 0x000 Reserved 0x004 Reserved 0x008 RW 2 0 fn_mod_bm_iss Bus matrix issuing functionality modification register This register is only present if the block is connected directly to a switch This register sets the issuing capability of the preceding switch arbitration scheme to 1 You can configure the register bits as follows 0 Read issuing read...

Page 45: ...ion You can configure the register bits as follows 0 Read issuing read_iss_override 1 Write issuing write_iss_override a The reset value is initialized to the tidemark value that you set in the configuration GUI in AMBA Designer ADR 301 Table 3 3 Registers for each AMIB continued Address offset Type Width Reset value Name Description Table 3 4 Address region control registers Address offset Type W...

Page 46: ...tting bits each bit position maps onto the region number For example the security1 5 bit is the security setting for the address region for master interface node number 1 region 5 0x18 0x10C WO 1 16 security n Slave n security setting It contain one bit for non virtual slaves and up to 16 bits for APB master interfaces 0x110 0xFFF RO Reserved Table 3 4 Address region control registers continued Ad...

Page 47: ...contiguous for example you could have a register named AMIB_0 in the region 0x4000 and have a register named AMIB_1 in the region 0xA000 0xFF4 RO 8 0xF0 Component ID1 Generic IP component class preamble 0xFF8 RO 8 0x05 Component ID2 Preamble 0xFFC RO 8 0xB1 Component ID3 Preamble Table 3 5 Peripheral ID registers continued Address offset Type Width Reset value Name Description ...

Page 48: ... an expander for data width changes Throughout the document r2p0 Global dynamic QoS instead of local static QoS Throughout the document r2p0 Internally programmable instead of externally programmed Throughout the document r2p0 System level address map replaces an address map for each interconnect Throughout the document r2p0 Extended timing closure options replace limited timing closure options Th...

Page 49: ...Revisions ARM DDI 0397G Copyright 2006 2010 ARM All rights reserved A 2 ID031010 Non Confidential Table A 2 Differences between issue F and issue G Change Location Affects No technical changes ...

Page 50: ...ect Advanced High performance Bus AHB A bus protocol with a fixed pipeline between address control and data phases It only supports a subset of the functionality provided by the AMBA AXI protocol The full AMBA AHB protocol specification includes a number of features that are not commonly required for master and slave IP developments and ARM recommends only a subset of the protocol is usually used ...

Page 51: ...erms word aligned and halfword aligned therefore stipulate addresses that are divisible by four and two respectively AMBA See Advanced Microcontroller Bus Architecture APB See Advanced Peripheral Bus AXI See Advanced eXtensible Interface AXI channel order and interfaces The block diagram shows the order in which AXI channel signals are described the MI and SI conventions for AXI components AXI ter...

Page 52: ...bility The maximum number of active transactions that a master interface can generate It is specified for master interfaces that use combined storage for active write and read transactions If not specified then it is assumed to be equal to the sum of the write and read issuing capabilities Read ID capability The maximum number of different ARID values that an MI can generate for all active read tr...

Page 53: ...e group of transfers can occur Bursts over AMBA are controlled using signals to indicate the length of the burst and how the addresses are incremented See also Beat Cache A block of on chip or off chip fast access memory locations situated between the processor and main memory used for storing and retrieving copies of often used instructions and or data This is done to greatly increase the average...

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