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PCI-1753/1753E
96/192-bit Digital I/O Card

User's manual

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Summary of Contents for PCI-1753

Page 1: ...PCI 1753 1753E 96 192 bit Digital I O Card User s manual ...

Page 2: ...ghts of third parties which may result from its use Acknowledgments PC LabCard is a trademark of Advantech Co Ltd IBM and PC are trademarks of International Business Machines Corporation MS DOS and Windows are trademarks of Microsoft Corporation Intel and Pentium are trademarks of Intel Corporation CE Notification The PCI 1753 1753E developed by ADVANTECH CO LTD has passed the CE test for environm...

Page 3: ... 2 1 Initial Inspection 10 2 2 Unpacking 10 2 3 Jumper Settings 11 2 4 Installation Instructions 14 CHAPTER 3 Operation 17 3 1 Overview 18 3 2 Digital I O Ports 18 3 2 1 Introduction 18 3 2 2 8255 Mode 0 18 3 2 3 Input Output Control 19 3 2 4 Initial Configuration 19 3 2 5 Dry Contact Support for Digital Input 20 3 3 Interrupt Functions 21 3 3 1 Introduction 21 3 3 2 IRQ Level 21 ...

Page 4: ...ing Edge Control 25 3 3 6 Interrupt Flag Bit 25 3 3 7 Pattern Match Interrupt Function 26 3 3 8 Change of State Interrupt Function 27 APPENDIX A Register Format of PCI 1753 1753E 29 A 1 PCI 1753 Register Format 30 A 2 PCI 1753E Register Format 31 APPENDIX B Pin Assignments of Cable PCL 10268 33 ...

Page 5: ...1 General Information CHAPT ER ...

Page 6: ...automatically controlled by software Dry Contact Support for Digital Input Each digital input channel at the PCI 1753 1753E accepts either 0 5 VDC wet contact or dry contact inputs This dry contact capability allows the channel to respond to changes in external circuitry e g the closing of a switch in the external circuitry when no voltage is present in the external circuit Reset Protection Fulfil...

Page 7: ...s with higher performance Cost Savings for Increasing the Number of Input Output Lines Industrial users are needing more and more digital I O lines to transmit data or to monitor control outside devices To meet this trend and to satisfy user s budget considerations Advantech has developed an extension board for the PCI 1753 called the PCI 1753E The PCI 1753E has almost the same structure as the PC...

Page 8: ... the interrupt Output status read back Pattern match and Change of state interrupt functions for critical I O monitoring Keeps I O setting and digital output values when hot system reset Supports dry contact and wet contact High density 100 pin SCSI connector 1 3 Applications Industrial AC DC I O devices monitoring and controlling Relay and switch monitoring and controlling Parallel data transfer ...

Page 9: ... mA sink Logic level 1 3 76 V min 24 mA source Transfer Rate 1 6 Mbytes sec tested under DOS K6 300MHz CPU Power Consumption 5 V 400 mA typical 5 V 2 7 A max Operating Temperature 0 60 C 32 140 F refer to IEC 68 2 1 2 Storage Temperature 20 70 C 4 158 F Operating Humidity 5 95 RH non condensing refer to IEC 68 2 3 Connector One 100 pin SCSI female connector Dimensions PCI 1753 175 x 100 mm 6 9 x 3...

Page 10: ...9 80 81 82 83 85 84 86 87 88 89 90 91 93 92 94 95 96 97 98 99 100 51 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PB20 PB20 PB22 PB23 PB24 PB25 PB26 PB27 PC21 PC20 PC22 PC23 PC24 PC25 PC26 PC27 GND PA31 PA30 PA32 PA33 PA34 PA35 PA36 PA37 PB31 PB30 PB32 PB33 PB34 PB35 PB36 PB37 PC31 PC30 PC32 PC33 PC34 PC35 PC36 PC37 VCC PA20 PA00 PA07 I O pins of Port A0 PA10 PA17 I O pins of Port A1 PA20 PA27 I O pins of P...

Page 11: ...Chapter 1 Gerneral Information 7 Figure 1 1 PCI 1753 1753E Block Diagram 1 6 Block Diagram ...

Page 12: ...8 PCI 1753 User s Manual ...

Page 13: ...Chapter 2 Installation 9 2 Installation C H A P T E R ...

Page 14: ...cking The PCI 1753 1753E contains components that are sensitive and vulnerable to static electricity Discharge any static electricity on your body to ground by touching the back of the system unit grounded metal before you touch the board Remove the PCI 1753 1753E card from its protective packaging by grasping the card s rear panel Handle the card only by its edges to avoid static discharge which ...

Page 15: ...re below for help in identifying card components Figure 2 1 Location of connectors and jumpers Jumper Settings to Set Ports as Input or Output by Software When the two pins of jumpers JPA0 JPB0 JPC0L JPC0H JPA1 JPB1 JPC1L JPC1H JPA2 JPB2 JPC2L JPC2H JPA3 JPB3 JPC3L or JPC3H are not shorted i e by setting a jumper the corresponding ports are set to be configurable as input or output ports by softwa...

Page 16: ...nt of a hot reset the settings and output values present at the port just prior to reset are restored to each port following reset This feature applies to both ports set by software and to ports configured as output ports via jumper Depending on the application this capability may allow a card to be reset without requiring a complete shutdown of processes controlled by the card since port values a...

Page 17: ...PC0H JPC1H JPC2H and JPC3H Jumpers for high nibble of ports C0 C1 C2 and C3 Sets port as an output port Sets port to be software configurable as input or output default JP1 Enables the reset protection function All ports return to the state held just prior to reset Disables the reset protection function All ports return to the default state for software set or to output port output low for jumper ...

Page 18: ...e PCI 1753E to control more than 96 I O points please find two adjacent 5V PCI slots Remove the screw that secures the expansion slot cover to the system unit Save the screw to secure the interface card retaining bracket 5 Carefully grasp the upper edge of the PCI 1753 Align the hole in the retaining bracket with the hole on the expansion slot and align the gold striped edge connector with the exp...

Page 19: ...E card by screwing the mounting bracket to the back panel of computer 7 Attach any accessories 100 pin cable wiring terminal board etc to the card 8 Replace the cover of your computer Connect the cables you removed in step 2 9 Turn the computer power on ...

Page 20: ...16 PCI 1753 User s Manual ...

Page 21: ...Chapter 3 Function Description 17 3 Operation C H A P T E R ...

Page 22: ...bility than a standard 8255 chip Each of these 8255 chip emulators has 24 programmable I O pins that are divided into three 8 bit ports The total 96 digital I O pins on either the PCI 1753 or the PCI 1753E are divided into 12 ports designated PA0 PB0 PC0 PA1 PB1 PC1 PA2 PB2 PC2 PA3 PB3 and PC3 Each port can be programmed as an input or an output port The I O pins in port A0 are designated PA00 PA0...

Page 23: ...put voltage will appear at the pins immediately following the control word taking effect If no output value was specified the value will be indeterminate either 0 or 1 which may cause a dangerous condition 3 2 4 Initial Configuration The initial configuration of each port depends on the input output jumper setting of each port on the setting of the jumper JP1 and on whether the power was actually ...

Page 24: ... the channel to respond to changes in external circuitry e g the closing of a switch in the external circuitry when no voltage is present in the external circuit Figure 3 1 shows external circuitry with both wet and dry contact components connected as an input source to one of the card s digital input channels Figure 3 1 Wet and dry contact inputs Note For wet contact configurations a malfunction ...

Page 25: ...ty and flexibility 3 3 2 IRQ Level The IRQ level is set automatically by the PCI plug and play BIOS and is saved in the PCI controller There is no need for users to set the IRQ level Only one IRQ level is used by this card although it has six interrupt sources 3 3 3 Interrupt Control Registers The Interrupt Control Registers Base 16 17 18 and 19 for the PCI 1753 and Base 48 49 50 and 51 for the PC...

Page 26: ...n 0 3 Fn interrupt flag bit of port Cn n 0 3 F01 pattern patch interrupt flag bit of port A0 F02 change of state interrupt flag bit of port B0 Base 16 48 Port 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 Abbreviation F0 E0 M01 M00 F02 M2 F01 M1 Base 17 49 Port 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Abbreviation F1 E1 M11 M10 Base 18 50 Port 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Abbreviation F2 E2 M21 M20 Base 19 51 Port 3 Bit D7...

Page 27: ... M 00 0 0 0 1 1 0 1 1 PC00 PC04 M 11 M 10 0 0 0 1 1 0 1 1 PC10 PC14 M 21 M 20 0 0 0 1 1 0 1 1 PC20 PC24 M 31 M 30 0 0 0 1 1 0 1 1 PC30 PC34 M 2 1 0 M 1 1 0 State change PB0 Pattern m atch PA 0 Q CLK D VCC IN T A Figure 3 2 Interrupt sources ...

Page 28: ...Base 49 determines the interrupt source of port C1 and so forth Please refer the table in Appendix A to find the corresponding address for the interrupt source control of each port C The following table shows the relationship between an interrupt source and the values in the mode bits Table 3 3 Interrupt mode bit values Base 16 48 Port 0 Base 17 49 Port 1 M01 M00 Description M11 M10 Description 0 ...

Page 29: ...he status of an interrupt It is a readable and writable bit Read the bit s value to find the status of the interrupt write 1 to this bit to clear the interrupt This bit must be cleared in the ISR to service the next incoming interrupt Table 3 5 Interrupt flag bit values F01 pattern patch interrupt flag bit of port A0 F02 change of state interrupt flag bit of port B0 Fn interrupt flag bit of port C...

Page 30: ... enabling a PC to handle more I O points with higher performance The following is an example Example 3 1 Assume that the pattern match function for the I O channels PA01 PA02 PA06 and PA07 of the PCI 1753 is enabled i e PA00 PA03 PA04 and PA05 on the PCI 1753 and port A0 on the PCI 1753E are ignored during the pattern match monitoring process The user can set the pattern match values for the enabl...

Page 31: ...d channels changes its state the PCI 1753 delivers an interrupt signal to the system to handle this event The following is an example Example 4 2 Assume that the change of state interrupt function for the I O channels PB01 PB02 PB06 and PB07 on the PCI 1753E are enabled i e the signals in PB00 PB03 PB04 and PB05 on the PCI 1753E and port B0 of the PCI 1753 are ignored during the change of state pr...

Page 32: ...rt A0 0 Disable the change of state interrupt function for port A0 b Then enable the change of state interrupt function for port B0 of the PCI 1753E by writing a 1 in bit 2 of Base 48 c When a change of state occurs in PB01 or PB02 or PB06 or PB07 on the PCI 1753E an interrupt signal is generated ...

Page 33: ...Appendix A Calibration 29 A Register Format of PCI 1753 1753E A P P E N D I X ...

Page 34: ... Port B3 Port B3 14 Port C3 Port C3 15 Port 3 Configuration Register 16 Interrupt Control Register for Port 0 Interrupt Control Register for Port 0 17 Interrupt Control Register for Port 1 Interrupt Control Register for Port 1 18 Interrupt Control Register for Port 2 Interrupt Control Register for Port 2 19 Interrupt Control Register for Port 3 Interrupt Control Register for Port 3 20 Pattern Matc...

Page 35: ...A3 45 Port B3 Port B3 46 Port C3 Port C3 47 Port 3 Configuration Register 48 Interrupt Control Register for Port 0 Interrupt Control Register for Port 0 49 Interrupt Control Register for Port 1 Interrupt Control Register for Port 1 50 Interrupt Control Register for Port 2 Interrupt Control Register for Port 2 51 Interrupt Control Register for Port 3 Interrupt Control Register for Port 3 52 Pattern...

Page 36: ...32 PCI 1753 User s Manual ...

Page 37: ...Appendix A Calibration 33 B Pin Assignments of Cable PCL 10268 A P P E N D I X ...

Page 38: ...PIN 02 PIN 03 PIN 04 PIN 05 PIN 06 PIN 07 PIN 08 PIN 10 PIN 09 PIN 11 PIN 12 PIN 13 PIN 14 PIN 15 PIN 16 PIN 18 PIN 17 PIN 19 PIN 20 PIN 21 PIN 22 PIN 23 PIN 24 PIN 25 PIN 50 PIN 01 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 18 17 19 20 21 22 23 24 25 27 26 28 29 30 31 32 33 34 1 36 37 38 39 40 41 42 44 43 45 46 47 48 49 50 52 51 53 54 55 56 57 58 59 61 60 62 63 64 65 66 67 68 35 PIN 27 PIN 28 PIN 29 PI...

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