Zynq UltraScale+, User Manual, Page: 26 / 70

RFSoC Data Converter Evaluation Tool User Guide 26
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 4
Clocking
The evaluation tool design has 256 MHz, 409.625 MHz, 300 MHz, and 512 MHz clock
domains. The RF-DAC output is a maximum of 409.625 MHz and RF-ADC 256 MHz. The
256 MHz output from ADC is supplied to the clocking wizard for generating 512 MHz for
driving the PL ADC path whereas 409.625 MHz drives the PL DAC path directly. The 300 MHz
clock is generated from the PL DDR block (ddr4_0).
Figure 4-1 shows the analog and mixed signal (AMS) clocking structure in the ZCU111
evaluation board.
The RF data converter clocking includes a primary external onboard reference PLL
(LMK04208) and onboard RF PLLs (LMX2594) to generate RF-ADC and RF-DAC sample
clocks. The primary management interface for the PLL devices is the Serial Protocol
Interface (SPI). The SPI is enabled on the ZCU111 via an I2C to SPI bridge. The bridge
components are enabled using the I2C MUX/Expander component present on ZCU111. This
X-Ref Target - Figure 4-1
Figure 4-1: ZCU111 AMS Clocking Structure
PS
I2C1
I2C0
I2C
Mux
I2C
SPI
I2C
Expander
LMK04208
LMX2594
PLL 3
LMX2594
PLL 2
LMX2594
PLL 1
SysRef In SysRef
RFSoC
To ADC Tile 0 - 1
To DAC Tile 0 - 1
To ADC Tile 2 - 3
FPGA REF CLK
SysRef FPGA
X21244-092118
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