Hardware Development Guide of Module Product
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MF206A
Figure 3–7 Module Serial Port & AP Application Processor
MF206A
AP
RXD
RXD
TXD
TXD
CTS
RFR
CTS
RFR
3.11
JTAG (Joint Test Action Group) Interface
3.11.1
Description of PINs
The JTAG interface complies with the ANSI/ICEEE Std. 1149.1-1990 standard, and the interface is defined as
shown in Table 3-10.
Table 3–10 Definition of JTAG Signal
PIN No.
Pin Name
I/O Type
Signal Description
3
JTAG_RESOUT_N
DI
LGA reset
72
JTAG_TRST_N
DI-PD
JTAG reset
73
JTAG_RTCK
DO
JTAG return clock
74
JTAG_TCK
DI-PU
JTAG clock input
75
JTAG_TDO
Z
JTAG test data output
76
JTAG_TDI
DI-PU
JTAG test data input
77
JTAG_TMS
DI-PU
JTAG test mode select
78
GND
--
Grounding