Z86C5000ZEM
CP95DZ80305
62
PRECAUTIONS
(Continued)
9.
Power Supply ramp-up/rise time must be such that
when minimum power-on reset time (T
POR
) expires,
then the V
CC
must be in the supported specified
operating range of the device.
10. The bits of non-implemented features (of devices
having a PCON register) must be set to "1" state on the
emulator.
11. Check the T
POR
and T
WDT
specifications of the device
that you wish to emulate. The actual specification may
differ from the ICE chip specifications.
12. The general-purpose registers after Power-On Reset
or at initial emulator use will be different than the actual
device. The emulator self test will always leave the
same values in the general-purpose registers, while
the real device will have a random/undefined value in
the general-purpose registers.
Z86C03/06/09/16
1.
Devices with the comparator output feature have the
P32 comparator output coming out of P35.
2.
For Z86C03/04/06/07/08/09/16/19/30/31 and Z86E03/
04/07/08/30/31, the register %F8 (PO1M register) bits
D4 and D3 must be set to state "0" and bit D2 must be
set to state "1."
3.
WDT Register (F) %0F should only be written in the first
64 internal system clocks from the start of program
execution.
4.
The PCON register on Z86C16 is not reset after
Stop-Mode Recovery.
5.
When using the C50 ICEBOX to emulate the C06, the
comparator outputs are at P34 and P37, which is
different than the C06, which is at P34 and P35.
Z86E04/E08/E07
1.
Z86E04 and Z86E08 have special features such that
programming the ROM protect mode will also put the
device in Low EMI mode, where XTAL frequency =
internal SCLK and all output drive capabilities are
reduced by 75 percent.
Z86E04/E08/E07
1.
The Z86C30/31/40/50/89/90 and Z86E30/31/40 have
the P32 comparator output coming out of P37.
2.
Reg (F) %00 PCON has D2 controlling the open-drain
for Port 0 and D1 controlling the open-drain for Port 1.
This is for the following:
Z86C30/31/40/50/89/90
Z86E30/31/40
3.
For Z86C03/04/06/07/08/09/16/19/30/31 and Z86E03/
04/07/08/30/31, the register %F8 (PO1M register) bits
D4 and D3 must be set to state "0" and bit D2 must be
set to state "1."
4.
WDT Register (F) %0F should only be written in the first
64 internal system clocks from the start of program
execution.
5.
For Z86C30/31, the "No Auto Latch" feature is not
implemented.
Z86C40/50/89/90 and Z86E40
1.
WDT Register (F) %0F should only be written in the first
64 internal system clocks from the start of program
execution.
2.
The Z86C30/31/40/50/9/90 and Z86E30/31/40 have
the P32 comparator output coming out of P37.
3.
Reg (F) %00 PCON has D2 controlling the open-drain
for Port 0 and D1 controlling the open-drain for Port 1.
This is for the following:
Z86C30/31/40/50/89/90
Z86E30/31/40
4.
For Z86C40, the "No Auto Latch" feature is not
implemented.
