ZiLOG Z80 series Page 122 Handbook Download

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Summary of Contents for Z80 series

Page 1: ...VM SD microcomputer handbook ...

Page 3: ...icrocomputer Handbook by William Barden Jr DISTRIBUTORS L P ENTERPRISES 313 K1rNNG1TON ROAD ILFCR Essex 1G1 1PJ E N G L A N D Tel 01 553 1001 Howard W Sams Co inc 4300 WEST 62ND ST INDIANAPOLIS INDIANA 46268 USA ...

Page 4: ...y is assumed with respect to the use of the information contained herein While every precaution has been taken in the preparation of this book the publisher assumes no responsibility for errors or omissions Neither is any liability assumed for damages resulting from the use of the information contained herein International Standard Book Number 0 672 21500 4 Library of Congress Catalog Card Number ...

Page 5: ...d with one instruction after initialization the one search instruction replacing four equivalent instructions in other microprocessors In addition to the Z 80 microprocessor itself Zilog has imple mented other devices to supplement the power of the Z 80 A PIO provides parallel I O with two 8 bit ports software configured I O vectored interrupt capability and automatic priority interrupt en coding ...

Page 6: ...to instruction set groups Many examples of each kind of operation are provided The last chapter of the section details some commonly used subroutines written in Z 80 assembly language The third section discusses microcomputers built around the Z 80 Chapter 17 covers Zilog products including the microcomputer board products in the Z 80 family and development systems Four other Z 80 microcomputer ma...

Page 7: ... Cycle Interrupt Request Acknowledge Cycle Nonmaskable Interrupt Request Cycle Exit From Halt In struction Memory or I O Wait States CHAPTER 4 ADDRESSING MODES 41 Implied Addressing Immediate Addressing Extended Immediate Addressing Register Addressing Register Indirect Addressing Ex tended Addressing Modified Page Zero Addressing Relative Ad dressing Indexed Addressing Bit Addressing CHAPTER 5 IN...

Page 8: ...tation Representation of Number Bases Ex pression Evaluation Pseudo Operations Assembly CHAPTER 10 MOVING DATA LOAD BLOCK TRANSFER AND EXCHANGE GROUPS 145 8 Bit Moves 8 Bit Moves Using HL 8 Bit Moves Using Index Reg isters 8 Bit Moves Using the A Register and Extended Addressing 8 Bit Moves Using the A Register and BC or DE Register Indirect 16 Bit Moves Immediate Loads of 16 Bits 16 Bit Transfers...

Page 9: ... GROUPS A Register I O Instructions I O Instructions Using C Register I O Block Transfer Instructions Software I O Drivers DMA Actions Interrupt Operations 219 CHAPTER 16 Z 80 PROGRAMMING COMMONLY USED SUBROUTINES 232 Comparison Subroutine Timing Loop Multiply and Divide Sub routines Multiple Precision Arithmetic Routines ASCII to Base X Conversions Base X to ASCII Conversions Fill Data Routine St...

Page 10: ...are The Digital Group Inc Digital Group Z 80 CPU Board Digital Group Memory Boards Digital Group I O Interfaces and Devices Digital Group Systems Digital Group Software Radio Shack Radio Shack Hardware Radio Shack Software APPENDIX A Z 80 ELECTRICAL SPECIFICATIONS APPENDIX B 8080 AND Z 80 INSTRUCTIONS COMPARED APPENDIX C Z 80 INSTRUCTIONS APPENDIX D BINARY AND HEXADECIMAL REPRESENTATION APPENDIX E...

Page 11: ...SECTION I Z 80 Hardware ...

Page 12: ...n of microprocessors from Intel retained the PMOS P channel metal oxide semiconductor fabrication tech niques of the 4004 but offered an 8 bit wide data bus and a larger instruction repertoire of 48 instructions Designated the 8008 the microprocessor had a faster instruction cycle time than the 4004 as data for both instruction execution and decoding and for operands could be handled in 8 bit slic...

Page 13: ...trange to many programmers the instruction set decidedly had moved away from one for pri marily control applications to one that was more general purpose in nature In 1976 Intel brought out several variations on the 8080 The Intel 8085 included a serial input output capability on the micro processor chip itself In addition the 8085 had a requirement of only a single phase clock the 8008 and 8080 w...

Page 14: ...0 A REGISTER FLAGS A FLAGS B C B C D E D E H L H L INTERRUPT VECTOR I MEMORY REFRESH R INDEX REGISTER IX IY STACK POINTER SP PROGRAM COUNTER PC 800818080 In addition to providing the eight 8 bit CPU registers of the 8080 the Z 80 duplicates the eight registers to offer sixteen registers Two index registers offer indexing capability not provided in the 8080 An interrupt vector register and memory r...

Page 15: ... eight The Z 80 Microcomputer Handbook is divided into three sections Section I covers the hardware aspects of the Z 80 Architecture in terface signals and timing addressing modes instruction set flags interrupt sequences interface of memory and I O devices and DMA operation are discussed When applicable differences between the 8080 and Z 80 are discussed Section II discusses Z 80 software grouped...

Page 16: ... addresses of input output devices The main path for data within the CPU is an internal data bus which connects the CPU registers arithmetic and logical unit data bus control and instruction register The arithmetic and logical unit performs addition subtraction logical functions of ANDing ORing and exclusive ORing and shifting operations between two 8 bit operands In addition binary coded decimal ...

Page 17: ...ge in the CPU is to be preferred over storage in memory as data can be accessed by a program much more rapidly from CPU registers than from external memory In a more sophisticated use of the block switching capability the unused set of registers may be used to hold the environment after receiving an interrupt This con cept will be discussed in a later chapter in this section Just as in the 8080 th...

Page 18: ...ers for example originally specified a High memory address of eight more significant bits and a Low memory address of eight less significant bits as shown in Fig 2 4 The same is true of the B C and D E registers In the 8080 the capability also was pro vided to allow the B C and D E to specify a memory address giving three register pairs that could hold a memory address pointer to data in memory In...

Page 19: ... bit operations would have to be performed if 16 bit arithmetic were not implemented Fig 2 5 shows the use of the register pairs in double precision operations 16 B IT RESULT ALU ADD SUBTRACT INCREMENT DECREMENT I f _f OPERAND ANDI OPERAND 2 _l t I B C REGISTER PAIR D E REGISTER PAIR H L REGISTER PAIR SP IX IY FLAG S Fig 2 5 Register pair double precision operation FLAG REGISTER The flag register ...

Page 20: ...l in a later chapter in this section Throughout this book the term flags flag reigster and condition codes will be used inter changeably SPECIAL PURPOSE REGISTERS The remaining CPU registers that are available to the programmer are the I R IX IY SP and PC registers Two of these registers are exactly the same as they are in the 8080 the SP or Stack Pointer and PC or Program Counter The PC register ...

Page 21: ... after the jump or branch to be automatically saved in the stack area This saves the location so that at some later time a return may be made back to the next instruction in sequence after the jump or branch Not only is the PC saved for certain types of jumps or branches but it is automatically saved for interrupts Here the address of the current instruction being executed is saved in the stack as...

Page 22: ...102 I I 0103 0100 0101 1 PUSH DATA A 0100 0101 0102 OA TAA 0103 2 PUSH DATA B 0100 0101 0102 0103 0100 0101 0102 0103 DATA B DATA A 3 PULL DATA B DATA C2 DATA C1 DATA A 14 PUSH DATA C TWO BYTES 0102 0103 0101 The effective address of the memory operand is obtained by adding the contents of the index register and a 16 bit value contained in the displacement field of the instruction employing the in...

Page 23: ...000H as shown in Fig 2 9 In general the I register holds the 8 most significant bits of an interrupt vector table which may hold interrupt vectors for 128 interrupting devices LOW ORDER 8 B ITS FROM DEVICE I REGISTER 1 1 1 1 1 1 1 1 1 L MEMORY LOCATION FF10 FF11 FF12 FF13 FF14 FF15 FF16 FF17 E005 E004 E003 E002 E001 E000 E 0 16 BITMEMORY ADDRESS FF14H 0 0 CONTENTS OF FF14 POINTS TO INTERRUPT PROCE...

Page 24: ...address bits equal to the R register can now be refreshed without fear of contention simultaneous read of the same memory cell by the Z 80 CPU The R register is normally not used by the programmer MICROCOMPUTER COMPONENT PARTS As in any microcomputer the microprocessor chip itself does not constitute the complete computer system Fig 2 10 shows the com ponent parts of a typical Z 80 system The Z 80...

Page 25: ...poration ASR 33 Teletype for example accepts data at the rate of 10 bytes per second While waiting for the Teletype to accept a byte of data the Z 80 microprocessor could be executing 1 10 second worth of instructions or about 30 000 instructions The Teletype controller allows the Z 80 to pass a byte in several microseconds and signals the Z 80 when the Teletype is done processing the data from th...

Page 26: ...s the user to interrogate memory locations change the contents of memory locations modify registers load and save programs on I O devices and other func tions If a control panel is present it performs the same functions as the monitor program by allowing the user to manually address examine and change data in CPU registers and memory The only advantage that a control panel would have over a monito...

Page 27: ...ernal memory of 6553610 or 64K may be addressed directly by the Z 80 CPU When I O devices are addressed the least significant eight lines of the address bus A7 AO hold the I O device address which may be 0 through 25510 In addition to memory or I O device addresses the least significant seven lines of the address bus hold the contents of the R or Memory Refresh Register for certain times during ex...

Page 28: ...operation DMA permits an external device to go directly to memory and transfer data between memory and the device The CPU must be locked out during a DMA operation to avoid the conflict of the CPU re questing memory service at the same time and from the same mem ory location as an external device When the external device brings down logic 0 the B L77TFQ Bus Bus Request signal the CPU responds with...

Page 29: ...mory six address line inputs would require sixty four separate refreshes 26 with the entire refresh cycle lasting no longer than 2 milliseconds When the output signal RFSH is low and signal TTROEQ is also low external dynamic memory will use the contents of the least significant seven bits of the address bus to implement one of the refresh cycles RFSH is active at every instruction fetch and since...

Page 30: ...AIT signal is low the CPU will mark time doing nothing while the external memory or I O device re sponds to a previous memory or I O request The WAIT signal en ables slow memories or rarely slow 1 0 devices to be interfaced to the Z 80 without buffering The HALT signal is an active low output signal that goes low during the time that a HALT instruction is being executed A HALT instruction in a pro...

Page 31: ...ORQ and M1 condition as an interrupt acknowledge Further actions taken for this interrupt are discussed later in this section CPU ELECTRICAL SPECIFICATIONS The electrical specifications for the Z 80 microprocessor chip are shown in Chart 3 1 All inputs and outputs are TTL compatible facilitating interfacing There is only one power supply voltage a 5 volt power supply The Z 80 microprocessor chip a...

Page 32: ...ymbol Parameter Min Typ Max Unit Test Condition VILe Clock Input Low Voltage 0 3 0 45 V Vine Clock Input High Voltage V m V V VIL Input Low Voltage 0 3 0 8 V Viii Input High Votlage 2 0 V V VOL Output Low Voltage 0 4 V IOL 1 8 mA Vox Output High Voltage 2 4 V Ion 100 µA Ice Power Supply Current 200 mA t 400 nsec ILr Input Leakage Current 10 µA VIN 0 to V ILOH Tri State Output Leakage 10 11A VOUT 2...

Page 33: ...the falling edge of T3 the memory operand is clocked into the CPU loading register R Ti M1 CYCLE T2 T3 LD R HU INSTRUCTION AO A15 MREQ RD WR DATA BUS DO D7 WAIT LD R HL EXECUTION Fig 3 4 Read cycle A memory write is shown in Fig 3 5 The instruction in this case is an LD HL R which takes the contents of the specified CPU register R and writes it into the external memory location pointed to by the H...

Page 34: ...cles long and from 10 to 20 T cycles 2 5 to 5 microseconds long for a 4 MHz clock The more sophisticated I O block transfer instructions INIR INDR OTIR OTDR transfer up to 256 bytes however and repeat machine cycles until all bytes have been transferred resulting in total instruction times that are dependent on the number of bytes to be transferred and the speed of the I O device Fig 3 6 shows an ...

Page 35: ...lable during the remainder of the write cycle and the external I O device controller will input it somewhere in this period Note that for both input and output cycles signal WAIT is inter nally enabled after T2 This causes the CPU to defer further I O processing until the WAIT line again is deactivated and effectively adds one clock cycle to the time of the input and output cycle This condition is...

Page 36: ...e CPU on the next rising edge of a T cycle and it will bring up or disable BUSAK on the next T cycle after that The CPU will then continue processing from the point at which it gave control to the bus requestor ANY M CYCLE 4 BUSRQ BUSAK AO A15 DO D7 BUS AVAILABLE STATES Tx T1 LAST T Tx Tx STATE SAMPLE SAMPLE MREQ RD _ ____ WE FLOATIN IORQ G RFSH Fig 3 8 Bus Request Acknowledge cycle INTERRUPT REQU...

Page 37: ...oller has had time to respond External memories must be capable of re sponding in a little over one T cycle or 250 nanoseconds for a 4 MHz clock while input output device controllers transferring data to the CPU have about two T cycles or 500 nanoseconds 40 ...

Page 38: ...operand may be specified in a variety of ways As an exam ple the ADD instruction adds two 8 bit operands One of the op erands is in the A register while the second can be in another CPU register Register Addressing an immediate value in the ADD instruction itself Immediate Addressing in memory and pointed to by the contents of the HL register pair Register Indirect Ad dressing or in a memory locat...

Page 39: ...ocation are fixed and no other register can be used CPL COMPLEMENT ACCUMULATOR BYTE 0 7 2FH OP CODE 0 10 0 1 0 1 1 1 1 Fig 4 1 Implied addressing in CPL instruction The format of the LD SP IY instruction is shown in Fig 4 2 Load SP with IY takes the 16 bit contents of the IY register and transfers it to the SP register The contents of the IY register re mains unchanged and no condition code bits a...

Page 40: ...The format of the XOR N instruction is shown in Fig 4 4 The contents of the A register are exclusive ORed with the second byte of the instruction and the result put into the A register The condi tion codes are set on the result of the instruction If the instruction were EE35H and the contents of the A register were 33H 35H and 33H would be exclusive ORed to produce 06H which would be put into the ...

Page 41: ... 0 0 1 0 In the register addressing mode one or more of the CPU registers is addressed by the instruction The instruction format would con tain a field s which would specify which CPU register s was to be utilized in performing the instruction Examples of this kind of addressing would be the RL R and AND R instructions The RL R instruction format is shown in Fig 4 7 The least sig nificant 3 bits o...

Page 42: ...STER R AND ACCUMULATOR 1 0 1 0 0 R Fig 4 8 Register addressing in AND R instruction tion with the least significant three bits of the byte specifying the register to be used in the instruction The coding of the registers is identical to the coding used in the RL R AND R takes the contents of the specified R register A B C D E H or L logically Alms it with the contents of the A register and puts th...

Page 43: ...of contiguous data is made simpler by instructions that automatically increment and dec rement by one the register pairs used as pointers The two proce dures for accessing blocks of random and contiguous data are shown in Table 4 1 along with the relative times Note that the examples are for illustrative purposes only to point out the deficiencies in register indirect addressing the Z 80 has more ...

Page 44: ... the memory address as a 16 bit address as one would expect Register Most Significant Least Significant Pair Byte Byte B C B C D E D E H L H igh L ow SP SP bits 15 8 SP bits 7 0 Register indirect addressing is primarily used for 8008 compatible instruction groups such as the 8 Bit Load 8 Bit Arithmetic and Logical and Rotate Shift groups EXTENDED ADDRESSING The extended addressing instructions hol...

Page 45: ... LOCATION NN WITH CONTENTS OF H L BYTE 0 BYTE 1 BYTE 2 0 0 1 0 0 0 1 0 NLS BYTE NMS BYTE 22H OPCODE Fig 4 13 Extended addressing in LD 116 BIT NN HL instruction ADDRESS Note that the 16 bit address in the instruction can address 216 or 65 536 memory locations The size of the address field in this instruc tion format together with the 16 bit width of the register pairs are the primary limitations t...

Page 46: ... of the instruction is one byte long reducing the instruction size from three bytes op code plus address to two bytes Page zero addressing allows addressing only of page zero relative addressing allows addressing of 256 memory locations grouped around the current instruction Fig 4 15 shows how this scheme is implemented The second byte of the instruction is a signed value of 12810 to 12710 1000000...

Page 47: ...exed addressing is an addressing mode that permits using the two index registers in the Z 80 IX and IY Many instruction groups permit using the indexed addressing mode and it is one of the most powerful features that the Z 80 offers The format of this addressing mode is shown in Fig 4 17 The op code of the instruction is in bytes 0 and 1 while the third byte holds an 8 bit signed displace ment of ...

Page 48: ... to provide testing setting or resetting any one of the 8 bits in an operand These operations would have to be performed by as many as three instructions in the 8080 or other computers An example of this is provided for the SET B IX D instruction shown in Fig 4 19 The SET instruction sets a specified bit and in this case the address of the byte containing the bit to be set is given by IX D an inde...

Page 49: ...D LD INNI HL LD INNI DD a LD INN IX LD NN IY LD SP HL LD SP IX LD SP IY PUSH QQ QQ IS BC DE HL AF PUSH IX PUSH IY POP QQ POP IX POP IY EX DE HL EX AF AF EXX x x EX SP HL EX ISPI IX EX ISPI IY LDI SEE CHAPTER 5FOR DETAILS z LL LDIR LDD W LDDR CPI CPIR CPD CPDR ADD A S ADC A S SUBS 00 SBC A S ANDS 0 ORS XOR S s s I CPS I NC S W1_ DEC S DAA CPL NEG CCF SCF NOP I LT Dl El IMO IM 1 IM 2 11 NOTE INSTRUC...

Page 50: ... B R JP NN JP CC NN JRE JR C E JR NC E JR Z E JR NZ E DJ NZ E DD IS BC DE HL SP g NN IS ADDRESS FIELD E IS DISPLACEMENT FIELD 2 CALL NN CALL CC NN RET RET CC RETI RETN RST P IN A N IN R ICI INI INIR IND INDR a OUT N A OUT ICI R OUTI OTIR OUTD OTDR P I S DOH 08H ETC N I S 8 B IT IMMEDIATE VALUE C I S C REG I STER NOTE INSTRUCTIONS AND ADDRESSING MODES USED IN THE 8080 ARE DESIGNATED BY A SINGLE LIN...

Page 51: ...truction groups The chart fol lows the same notation as has been used in the above description BEFORE REGISTER C AFTER t o 1 0 1 0 0 0 0 OOOOOOOo 1 1 0 1 1 1 1 1 1 0 0 0 1 0 0 1 0 01010001 t o 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 BIT SET Fig 4 20 Bit addressing example INSTRUCTION SET 0 C SET 4 C SET 5 C SET 7 C and that will be used in a discussion of the various instruction meth ods in ...

Page 52: ...Shift 8 Bit Set Reset and Test 9 Jump 10 Call and Return 11 Input and Output 8 BIT LOAD GROUP The 8 Bit Load Group is shown in Table 5 1 About half of the instructions in this group load an 8 bit value into a CPU register from another CPU register immediate value in the instruction or memory location The other half of the instructions store an 8 bit value from a CPU register or immediate value int...

Page 53: ... o o o i V N N O Q N P P O P Z U H w d Z u cV N o Lo N LO ch h X r Q N c 4 cq co N O I O O 1 O I I I O I O I o 0 oao oy oy o oy o yy o o x Z N Q N U n m d 2 X o y o y o E c O y y J J x X 0 E X c X r X 0 0 0 0 J J J J J O D J J 0 J 0 J 0 J 56 ...

Page 54: ... N Cl M N Cl N N p T T 0 0 O_ O O O O O O T T T T O O O O O O 0 c c 0 cc 2 2 C c c O 0 0 0 0 0 0 0 0 0 0 0 O D O O p Op 0 0 o 0 0 0 0 O 0 0 H H LL H H u w C a a Q a C a a aaa m c a a C m Q a a a v a m o 5 a Q d 0 0 0 0 0 0 0 0 0 0 0 a v 57 ...

Page 55: ...X D LD R IY D None of the condition code bits are affected after the load LD S R does the opposite of LD R S that is the contents of a CPU register R is transferred to a memory location using either an HL register pointer method of addressing LD HL R or indexed addressing LD IX D R or LD IY D R This is in fact a store kind of in struction called a MOV in the 8080 and 8008 LD S N is similar I I LD ...

Page 56: ...rates the various addressing modes and instruction types LD HL 1025H INSTRUCTION LD HL 1025H 0 0 1 0 0 0 0 1 8 BITS LD NNI IX INSTRUCTION MEMORY 5020 H 5021 H STACK POINTER REGISTER LD INN IX 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 M 20H 50 H HIGH ORDER LOW ORDER 25H 10H LD SP HL CPU H REGISTER CPU L REGISTER HIGH ORDER LOW ORDER I MEMORY ADDRESS 5020H 8BITS IX REGISTER 8 BITS 8 BITS 8 BITS Fig 5 2 Sixtee...

Page 57: ...to Z O N m O m M Q Q m v Q Q M Z O T T T T T T p T T p T T p T T p p T p 1 I I C O O O S O O C C y D C C O O C C C C O C C O C C O C C O O C C O 10 C 0 c r x z N yi LL N v C c C C C W q c v S S O y y y s N X Y x a x a X X x a Y c c O S J p O S S O C C C C C C C J J J J J J J J 60 ...

Page 58: ...o T T g g o 0 0 0 0 o g o 0 oco c c o c p c 0 c c a S o a 0 p 0 _ 6 O _ Q O cc o X x CY a X X 6 v X y v v C 4 C4 C14 v v E 1 1 1 1 1 1 c c vv c c SS c c SS y CL CL 1 LL x a o MM LLO LL x a x a XX x r x r 0 X X r c 2 J a a In a s x x to In IL O O O 0 0 J 0 J 00 J J 0 J LL LL LL LL LL 0 61 ...

Page 59: ... N N N N N CV Z co O O O O O O O O O O 0 N 0 0 0 O 0 0 O O 0 0 O U e M O 0 _ O a a y O O 0 0 0 O O O O O 0 0 O O O n 0 S O O O Z O O O N OH O OH N U U S a I t I O N O Q S N N N S W J U S w C S m V S l N v O x m Q 0 D 2 co oQ3 Xx OSm eo m 0 m m x ce C J L x X O x Q C W LL 0 Q X p D O N N 0 X X X w w w X w X X w w 0 0 0 62 ...

Page 60: ...Q Q N N N N N N N N O S O Q c O 63 0 0 O S O S O O O O O 0 p O H H H H 0 O H H H H OH QH QH OH O O H e H O H O H o I I c I _ 2 m 2 S m to 2 2 2 0 2 2 m m 2 2 2 0 O yy all Icy I all 11 I u IyL cL J V V m W W J V V m J J V m V m K Q in 2 a0 C Q co Q S in G m 0 in d Qx co 0 0 J 63 ...

Page 61: ...sters and exchanges between the two sets of registers see Table 5 3 CPU D REGISTER E 8 BITS CPU H REGISTER Fig 5 3 EX DE HL instructions EX DE HL simply exchanges the contents of register pairs DE and HL in the current set of registers as shown in Fig 5 3 EX AF AF however exchanges the contents of the A register and flag register of the current set of registers and the inactive set of registers as...

Page 62: ...8AH IY LOW ORDER J MEMORY 128AH TOP OF STACK 128BH 1EE TOP OF STACK 1 Fig 5 5 EX SP instructions LDI LDIR LDD and LDDR are four block transfer instructions that use register pairs BC DE and HL All four instructions trans fer a block of data from one place in memory to another The block may be 1 to 64K bytes Register pair BC must be preset with the number of bytes to be transferred register pair HL...

Page 63: ... LD I Fig 5 6 LDI and LDD instructions LDIR and LDDR perform identical functions to LDI and LDD with a supplemental action If the byte count is not zero P V flag set then the instruction continues transferring data until the byte count is 0 This means that there will be N executions of an LDIR or LDDR where N is the initial value of the BC register LDIR and LDDR are automatic transfers of a block ...

Page 64: ...ACTIONS REPEATED 3 ADD 1 TO DE N TIMES WHERE N 4 SUBTRACT 1 FROM BC IN BC INITIALLY 5 IF IBC i 0 GO TO STEP 1 6 GO ON TO NEXT INSTRUCTION LDDR ACTIONS 1 TRANSFER BYTE 2 SUBTRACT 1 FROM HL THESE ACTIONS REPEATED 3 SUBTRACT 1 FROM DE N TIMES WHERE N 4 SUBTRACT I FROM BC IN BC INITIALLY 5 IF IBCI j 0 GO TO STEP 1 6 GOON TO NEXT INSTRUCTION Fig 5 7 LDIR and LDDR instructions ing address of the block C...

Page 65: ...ACT 1 FROM HL 3 SUBTRACT 1 FROM BC 4 COMPARE BYTE TO A AND SET FLAGS 5 GOON TO NEXT INSTRUCTION Fig 5 8 CPI and CPD instructions 8 BIT ARITHMETIC AND LOGICAL GROUP The 8 bit arithmetic and logical instructions are used to add sub tract AND OR exclusive OR or compare two 8 bit operands one of which must be in the A register The second operand may be an immediate operand may be in another CPU regist...

Page 66: ...adds SUB S subtracts the second operand from the contents of the A register while SBC A S sub tracts the second operand and the current state of the carry from the contents of the A register The add and subtract instructions are shown in three addressing mode examples in Fig 5 10 There are two additional instructions in this group the INC S and DEC S instructions They increment or decrement the co...

Page 67: ... m T n O O sot o A o ooo aooa o 2O n 0 y 0 o y o y y o o o 2 HH HH H HHHHHHHHHH Z 00 00 O O 0 0 0 0 0 0 N v H H HH H HHHHHHHHH H W e a a a N HH H HHHHHHHHHH V H H H H H H H H O O O H 4O J ll V o c x I v E I I x y No aa aQ a aaaa Q X 11 yy y yyyyyyly x Qa Qa a aaaaaa 0 EE c xx N N N N xx C no in u N V U Z on as an as o Q co z 0 O U QCn n O xo ZZz 70 ...

Page 68: ...15 o o 0 v o o o 81 0 E t o o I I lal 0 C 0 Am m L w X o y C L udiL 0 m O L O c E v a v C d y L EL c m o E rnC h o v _ I 0 ou Mar v O L is C N ECOL 0 ti 0 O Y 0 0 C C w O C w a o a o 0 0 a E zIIII Z 0 o v A H Z 71 ...

Page 69: ...Condition codes are set as shown in Table 5 4 ADD A B T 8 BIT RESULT ALU ADD CPU B REG ADC A IHLI SBC A IX DI Fig 5 10 Add and Subtract instruction examples Two of the instructions in this group operate on the carry CY flag of the condition codes SCF sets the carry flag to a 1 CCF com plements the current state of the carry a 1 is set to a 0 and a 0 is set to a 1 These instructions are useful in s...

Page 70: ... interrupts by resetting or setting the interrupt enable flip flops IFF1 and IFF2 IM 0 IM 1 and IM 2 set interrupt modes 0 1 or 2 The meaning of the various modes is discussed in Chapter 7 CPL A BEFORE INSTRUCTION 1 0 1 1 0 1 1 0 74 Os is 1s Os A AFTER INSTRUCTION 0 1 0 0 1 0 0 1 73 NEG A BEFORE INSTRUCTION 1 0 1 1 0 1 1 0 74 as 1s 1 1s as 0 1 0 0 1 0 0 1 1 A AFTER INSTRUCTION 1 0 1 0 0 1 0 1 0 74...

Page 71: ...m O N O7 Q V v co O7 CS Z N 0 Y O 6 v N N N N Z O N N N N O Z co o O N 0 0 O O O O 0 O p 0 O S O o o 20 22 080 02 a 08 8 O n 80 80 o g o g o o o o S H H x O z 0 O N H H W CL N H H V H H H c a c m o I IU I O y 0 0 0 0 o N c c y O L y c o A O Np C C 0 w t o U u a0 Q Q o a uzL E E E O Q ULL d O N a z v LL zo o LL _ 74 ...

Page 72: ...f the operation into bed results Bed addition will be discussed in detail in Section II ADD HL SS 0 0 S 1 0 0 1 Fi 5 13 Sixteen bit arithmetic g register encoding 00 BC 01 DE 10 HL 11 SP 16 BIT ARITHMETIC GROUP All of the instructions in this group operate on 16 bit double precision values in either register pairs BC DE or HL or in 16 bit SBC Ht SP 1 1 1 0 717 0 1 0 1 1 1 0 01 0 ADD IX IX 1 1 0 1 ...

Page 73: ... N N N N N N N Z ou 8 m N o 0 o o O O O O O O a o o o 0 o oo oo o o o o a 0 r o o 0 8 e 8 8 c c X X X X X X Z O O 0 O a h H H na CL N H H V H H H H H U U V O Q E N 2 2 X a _X y X J 2 J 2 2 X y X X w V Q q o _ r N X y x e o o o v v v w w w a a n 13 a a z z z o 0 0 76 N L ...

Page 74: ...the HL register The condition codes are set as shown in Table 5 6 and an example of the instructions is shown in Fig 5 14 ADD IX PP and ADD IY RR permit addition of BC DE SP or the same index register to IX and IY respectively The condition codes are set as listed in the table and an example of the instruction is shown in the figure ROTATE AND SHIFT GROUP The instructions in this group include the...

Page 75: ...m m Z Q Q Q m N N o Z r N Q O p o U m Z p co N N Q Q 0 04 Q C C 0 G Y o o _ o p p _ p O O o O _ p O O O O 1 V 00 0 00 00 o 00 o x 0 0 0 0 0 0 0 0 z o o 0 0 0 0 0 0 N N H H H H i a a a CL N H H H H U H H H H H H H H o C0 7 r L O 1 O 0 v X 1 x Ad a e t a u E v c INI V t D n t E d Q x V v v cC J J eY J J J y J J K L Ix De Y Y L 09 CL ne 78 ...

Page 76: ... U U S F S c o Ln o m m H D m D 10 h CV n 0 0 a a o 00 00 0 0 O O O O O O O O O O O O O O H H H H H H H CL a a a a a a H H H H H H H H H H H H V C 0 O J ch O 0 O 0 _0 v i i X x X i X 2 J n S J 2 J 2 n v 2 O O C LY III III V III III III v v U e N N N N V oe i g a oe N n N Of o a S 79 ...

Page 77: ... shifted out from the A register going into the carry All four shifts are shown in Fig 5 15 Two shifts of this group RLD and RRD operate on the contents of a memory location addressed by register indirect addressing HL and the A register and shifts four bits at a time These two shifts are implemented to facilitate bcd operations where each bcd digit is made up of four bits If the reader considers ...

Page 78: ...t as shown in Fig 5 17 but does not retain it on a left shift RLC S OPERAND RL S RRC S RR M 8 B ITS 9 BITS Fig 5 18 RLC RL RRC RR instructions Any of the seven current CPU registers can be shifted when register addressing is used with the R field specifying the register as shown in Fig 5 17 The condition codes are set as listed in Table 5 6 In struction SRL S performs a logical right shift with a ...

Page 79: ... O C S ooogoo Z C4 w N N co LO C N e 0 Z N co to vl N O 0 v Z p N N Q N N m G N O O O O O T p p T O p p p p T 0 O S O S S O 0 O O 00 0 O 0 0 p _ Z o O o o N X X X X X X X X N H H H H v o o v a Ix 0 ga y y y X N N N _ _ X r X m F C m a0 m t co ti Cl W W N Cl 82 ...

Page 80: ...M N 10 V UI 83 ...

Page 81: ... to be operated on as follows BIT B 0 000 1 001 2 010 3 O11 4 100 5 101 6 110 7 111 BIT B R tests the bit and sets the Z flag if the bit is a zero and resets the Z flag if the bit is a 1 SET sets the indicated bit and does SET 7 D 0 1 0 1 1 1 1 1 D BEFORE INSTRUCTION 1 1 0 1 1 1 1 1 D AFTER INSTRUCTION RES S IHLI MEMORY OPERAND BIT 0 I IX DI BIT 0 IX D INSTRUCT ION MEMORY OPERAND 1 1 0 1 1 1 0 1 1...

Page 82: ...O O tt w O 0 N n N N 1 N N z M M co N M N M N M N o u O M M N N N N N N N N co TT TT 0T T T gT oT o 0 c r c c C4 o l C4 I C4 I C4 o f C4 g l co a oy s z a N LL N u G C C u N N 0 d o q cu c a H d U O O U d O O O y U No y C C CL Il E 11 y 11 S 11 y it E it y 11 U C U C U U U s C U 0 U U 0 u 0 a o a a u a uu a u C d G E c c C u w d U U z d N N Z a a a o a cc 85 ...

Page 83: ... Returns effect the transfer back to the instruction fol lowing the call by popping the stack and restoring the contents of the top of stack to the program counter Calls and returns are used for subroutine processing Subroutines are segments of code ranging from several instructions to hundreds of instructions that are called from many parts of a program This avoids redundancy in writing the subro...

Page 84: ...is set or reset re spectively The DJNZ E instruction is unique in that it decrements the contents of the B register If the result is nonzero the jump is performed if zero the next instruction in sequence is executed The two call instructions in this group also appear in the 8080 and 8008 CALL NN is an unconditional call and CALL CC NN condi tionally calls the subroutine at address NN The condition...

Page 85: ... as any unconditional call The jump is made to one of eight page 0 locations based on the T field of the RST P as shown in Fig 5 22 INPUT AND OUTPUT GROUP The last grouping of Z 80 instructions Table 5 10 is the Input and Output group The instructions in this group allow for transfer of 8 bit bytes of data to and from CPU registers A B C D E H or L with any of 256 possible I O device addresses spe...

Page 86: ... be tested by the conditional jumps described in Chapter 5 The condi tional jump effectively tests the results of arithmetic logical shift I O or other operations preceding the conditional jump The H and N flags are used to facilitate decimal or bed arithmetic operations Z FLAG The Z flag bit position 6 is set if the result of certain instruction executions was zero The Z flag will be set if the r...

Page 87: ...I 0 otherwise reset INIR INDR Set OUTI OUTD Set if B 1 0 otherwise reset OTIR OTDR Set As the table shows the Z flag is affected principally for arithmetic logical and shift operations Loads and stores have no effect on the Z flag except for the two cases of LD A I and LD A R The search group is essentially a comparison or subtraction and the Z flag is also affected here The bit test group is effe...

Page 88: ...result The S flag is affected by the instructions shown in Table 6 2 Sign flag actions are very similar to zero flag actions as shown in the table The sign flag is primarily affected by arithmetic and shift operations including the comparisons in the search group Note that for some instructions the flag is affected but that the state is not known The same ground rules on testing of the sign flag a...

Page 89: ...wise reset Load Group LD A R Set if R register is negative otherwise reset Search CPI CPIR Group CPD CPDR ADD A S ADC A S SUB S SBC A S 8 Bit AND S Set if result is negative otherwise reset Arithmetic OR S Group XOR S CP S INC S DEC S General DAA Set if msb of A 1 otherwise reset Purpose Arithmetic NEG Group 16 Bit ADC HL SS Arithmetic Group SBC HL SS RLC S Set if result is negative otherwise rese...

Page 90: ...arry from bit 15 otherwise reset 16 Bit ADC HL SS Arithmetic SBC HL SS Set if no borrow otherwise reset Group ADD IX PP Set if carry from bit 15 otherwise reset ADD IY RR RLCA Set from A bit 7 RLA RRCA Set from A bit 0 RRA Rotate RLC S Set from bit 7 of operand and S Shift RRC S Set from bit 0 of operand Group RR S SLA S Set from bit 7 of operand SRA S Set from bit 0 of operand SRL S Set from bit ...

Page 91: ... 16 B ITS 11101010 Fig 6 3 Carry in multiple precision operations PARITY OVERFLOW FLAG The parity overflow flag bit position 2 in the flag register is a dual purpose flag In the parity case the flag is set to represent odd parity or the result of the operation Odd parity occurs when the sum of the eight bits of the result is even In this case the parity bit is set If the sum is odd the parity bit ...

Page 92: ...reset Set if operand was 7FH before increment INC S otherwise reset Set if operand was 80H before increment DEC S otherwise reset General DAA Set if A parity even otherwise reset Purpose Set if A was 80H before negate other Arithmetic NEG Group wise reset 16 Bit Arithmetic ADC HL SS Set if overflow otherwise reset SBC HL SS Group RLC S RL S RRC S Rotate and RR S SLA S Set if parity even otherwise ...

Page 93: ...t 4 CPS otherwise reset Set Set if carry from bit 3 otherwise INC S Reset reset Set if no borrow from bit 4 DEC S otherwise reset Set DAA Indeterminate Not affected l G CPL Set Set enera Purpose Set if no borrow from bit 4 Arithmetic NEG otherwise reset Set Group CCF Not affected Reset SCF Reset Set ADD HL SS Set if carry out of bit 11 other ADC HL SS wise reset Reset 16 Bit Arithmetic SBC HL SS S...

Page 94: ...ions H repre sents the half carry from the four least significant bits of the result least significant bcd digit and N is the subtract flag which is set to indicate whether an add or subtract was last executed Table 6 5 shows the instructions affecting the H and N flags Note that in the general case an add instruction resets the N flag and a subtract sets the N flag This is also true for increment...

Page 95: ... 6 TO BOTH BCD DIG ITS 1 1001 1000 98 BCD WITH CY 1 CORRECT Fig 6 6 Bcd addition and use of CY and H Some examples of the above are shown in Fig 6 6 For a subtract N 1 a binary result must be corrected by subtracting a six from a bed digit position under certain conditions If there is a half carry a six is subtracted from the least significant bed digit position If there is a carry a six is subtra...

Page 96: ... 0010 72 BCD WITH CY 0 CORRECT SUBTRACT 91 FROM 19 IN BCD 0001 1001 19 BCD CY 1001 0001 91 BCD 1 1000 1000 88 BCD WRONG CY 1 H 0 CY 0110 0000 ADJUST BY 6 TO HIGH ORDER BCD DIGIT 1 0010 1000 28 BCD WITH CY 0 CORRECT SUBTRACT 99 FROM 11 IN BCD 0001 1001 CY 1001 1 1 M 0111 0110 0001 0001 11 BCD 99 BCD 1000 78 BCD WRONG CY 1 H 1 0110 ADJUST BY 6 TO BOTH BCD DIGITS 0010 12 BCD WITH CY 0 CORRECT Fig 6 7...

Page 97: ...yte will be available every 1 500 second or 2 milliseconds If the program that reads data from the paper tape reader is implemented without interrupts it will read a byte of data by an IN instruction every 2 milliseconds and the entire read operation will take approximately 2 5 microseconds as shown in Fig 7 1 For the remainder of the time the program is simply continually querying the paper tape ...

Page 98: ...cond use of interrupts is to provide CPU timing functions It is convenient to provide measured time intervals to the CPU to enable the CPU to maintain a real time clock for system time out functions or time of day indications Typically the time interval is provided via interrupts with a programmable counter timer inter face that interrupts the CPU every tenth of a second or so The CPU will recogni...

Page 99: ...errupts enabled or reset by the EI or DI instructions The INT interrupt action is more complicated than the NMI action since an external device must provide encoded data relating to the identification of the interrupting device In addition there are three different inter rupt mode for the maskable INT interrupt modes 0 1 and 2 that are set by instructions IM 0 IM 1 IM 2 Each mode provides a dif fe...

Page 100: ...MI INTERRUPT PROCESSING MEMORY LOCATION INSTRUCTION 0066H EX AF AF EXCHANGE AF OD67H EXX EXCHANGE OTHERS SP OTHER INTERRUPT PROCESSING 00AOH EX AF AF RESTORE AF 0OA1H EXX RESTORE OTHERS OOA2H REIN RETURN Fig 7 2 NMI interrupt processing instructions Interrupt processing now proceeds for the NMI condi tion The size of the interrupt processing routine is dependent on the amount of processing to be p...

Page 101: ...ns MASKABLE INTERRUPT MODE 0 Interrupt mode 0 is the default CPU interrupt mode on start up When signal RESET initially becomes active mode 0 is set in the CPU Mode 0 may also be set by execution of an IM 0 instruction Interrupt mode 0 is identical to the interrupt processing in the 8080 If mode 0 is set and the interrupt enable flip flop IFF1 is set and an external maskable interrupt occurs the f...

Page 102: ... pushing the contents of the program counter 3332H into the stack and transferring control to page 0 location 20H At 2014 a JP FEEOH is executed to transfer control to the paper tape interrupt 1 NEXT FRAME I PAPER TAPE READER CONTROLLER 6 RETURN TO 3332H SP SP l 3 SAVE LOCATION J OF INTERRUPT 4 INTERRUPT PROCESSING AT 20H MEMORY LOCATION INSTRUCTION 0020H JMP FEEOH A PAPER TAPE INTERRUPT PROCESSIN...

Page 103: ...ce When many devices are capable of interrupting some means of pri oritizing the devices must be implemented to avoid simultaneous interrupt requests from two or more devices over the same inter rupt line If a prioritizing scheme is not used confusion will result as each device thinks that it has received an interrupt acknowledge In a prioritizing scheme each device is assigned a priority from hig...

Page 104: ...nterrupt is that no external logic is required to jam the Restart onto the data bus at the proper time An external interrupt can be implemented with only enough logic to bring INT active and recognize the inter rupt acknowledge Of course only one interrupt level is permitted in this mode MASKABLE INTERRUPT MODE 2 The last and most powerful interrupt mode is interrupt mode 2 This mode allows up to ...

Page 105: ...g the address computed in step 3 6 The PC is loaded with the contents of the interrupt vector table entry to effectively cause a jump to the interrupt servicing routine defined by the address vector in the table Fig 7 6 shows an example of this process The interrupt vector table is located at F000H The table has ten entries of two bytes each defining ten interrupt servicing routines for the ten in...

Page 106: ...ed with the return address from the stack Note that the interrupting device could supply any eight bits for the vector not necessarily that address associated with its I O device address in the execution of IN and OUT instructions al though it is convenient to have device address 0 associated with table entry F000 device 1 associated with table entry F002H etc Note also that the interrupting devic...

Page 107: ...PIO automatically jams the proper 8 bit mode 3 vector onto the data bus to vector the interrupt to the proper memory location At the end of interrupt servicing the RETI is detected by decoding the instruction op code and the interrupt for the current PIO is completed IEO for the cur rent PIO is brought high enabling interrupts from lower priority devices A prioritizing scheme such as the above not...

Page 108: ... Finally device 0 interrupts during the middle of the interrupt proc essing routine for device number 1 causing interrupt 0 processing routine at 4000H to be entered This routine is completed by an RETI and the processing routine at 3000 is reentered This routine is then completed and after the RETI the processing routine at 1000H is again reentered Finally the lowest level processing rou tine at ...

Page 109: ...s to reset restart the system 4 ROM or PROM memory to contain the program 5 I O interfacing and devices 6 the Z 80 CPU Fig 8 1 shows a minimum system with the above components A momentary switch resets the CPU and starts program execution at location 0 by bringing down the RESET signal to a logic 0 As the reader will recall from Chapter 3 the RESET signal disables inter rupts sets the I and R regi...

Page 110: ...four flip flops are set by DO D3 when an output operation is performed When the RESET switch is pressed the RESET input goes low initializes the CPU and starts program execution at location 0 of the ROM The ROM program is accessed by making memory requests MREQ and RDs as no memory writes are possible of course with a read only device For this particular ROM bringing both chip select CS inputs to ...

Page 111: ...dditional external logic INTERFACING ROM AND RAM A more usable system with ROM or PROM and RAM memory and limited I O capability is shown in Fig 8 2 A larger ROM 1K x 8 is used to provide 1024 bytes of program area Two 256 x 4 bit high speed RAMS no WAITS necessary are used to pro vide 256 bytes of read write storage of dynamic variables The RAM and all system components are three state devices to...

Page 112: ...5 06 CPU D6 07 D7 08 Irol RD 1102 1103 WR 1104 256X4 RAM IORQ AO A7 AO A7 Ml RD R W CE MREQ A15 WR QUAD LATCH CP D I SABLE G2 TRI STATE BUFFERS AO A7 1 01 102 1103 1104 AO A7 RIW CE IROQ MI RD Fig 8 2 Z 80 interfacing with RAM and ROM 256X4 RAM t OUTPUTS TO 1 EXTERNAL t DEVICE INPUTS FROM EXTERNAL DEVICE 119 ...

Page 113: ... as in the previous example When an IN instruction is executed IORQ and M1 become active and the WR signal is also active Data bus outputs D3 DO are latched into the output latches during the output cycle When an OUT instruction is executed RD goes active and enables the program to sample the input data lines 10 13 The for mat of the output and input data is shown in Fig 8 4 Data bits seven throug...

Page 114: ...t address on the data bus from the R register Since the R register is continually sequencing from 0 to 255 in modulo 28 fashion every M1 cycle a new refresh address is continually available to the dynamic RAM memory Fig 8 5 shows a 4096 byte memory made up of eight 4096 by 1 dynamic RAMs Each RAM has 12 address inputs split between six row inputs and six column inputs The requirements for refresh ...

Page 115: ...e Fig 8 6 Two 8 bit I O ports are provided They can be programmed for either input or output transfers In addition to the two sets of eight bidirectional data lines A7 AO and B7 BO there are two sets of two control lines used for handshaking between the I O device and the PIO A RDY and A STB discussed later Data is transferred between the PIO and the Z 80 CPU by data bus lines D7 DO Six control li...

Page 116: ...ORT B S A EL CONT T EL CHIP AT IORQ RD INT INTERRUPT CONTROL ITEI IEO Z 80 P I O F4 A6 r A7 PORT A 110 LINES A RDY PORT A 4A s T B HANDSHAKE BO B1 B2 B3 PORT B B4 I O LINES B5 B6 87 B RDY B STB 1 PORT B HANDSHAKE t 1 5 GND Fig 8 6 PIO interface signals TO EXTERNAL 110 DEVICE S Internally the PIO appears as shown in Fig 8 7 Each port of the PIO has a number of registers associated with the port The...

Page 117: ...r 3 Mode 0 is the output mode of the PIO In mode 0 the 8 bit data output latch is active and the 8 bit data input register is in active Data may be written to the data output register by address ing the port and transferring eight bits of output data via an OUT instruction Data may also be read back from the port by an IN in struction although normally this would not be done as the program would a...

Page 118: ... using an IN instruction with an I O address of the PIO port 4 RDY line is set by action of IN instruction causing external device to ready next byte of data The actions in mode 1 are repeated for each byte of data to be read in The input operation is initiated by an IN instruction in which the data is ignored as the RDY line is set for the first time PIO MODE 2 PIO mode 2 is the bidirectional dat...

Page 119: ... TO PORT I O LINE 5 CORRESPONDS TO PORT I O LINE 6 CORRESPONDS TO PORT IA LINE 7 Fig 8 9 PIO mode 3 input output programming PIO INTERRUPTS Each port of the PIO may be programmed to provide an external interrupt to the Z 80 CPU for input or output operations When an OUT instruction with the port address is executed and the 8 bit con trol word shown in Fig 8 10 is output to the PIO port any subse q...

Page 120: ...l bits must go to an active set high or low before an interrupt is generated If bit six is a 0 any bit in the active state will generate an interrupt The port lines that are monitored for the AND or OR condition are fur ther defined for a mask If bit four is a 1 after the interrupt control word has been received by the PIO then the next word sent to the PIO must be a control word mask which is loa...

Page 121: ...y low Interrupts for port A would vector to the address specified in FFOOH and interrupts for port B would vector to the address specified in FF02H as described in Chapter 7 The above description illustrates the interfacing for one Z 80 PIO The configuration shown could be used for a variety of uses includ ing Teletype I O keyboard decoding high resolution a to d or d to a I O and 16 line process ...

Page 122: ...SECTION II Z 80 Software ...

Page 123: ......

Page 124: ...ram is employed The assembler provides an easy way to automatically assemble machine language instructions from a higher level symbolic assembly language MACHINE LANGUAGE Machine language is the most rudimentary form of any program It consists of the actual machine language operation codes and oper ands necessary to implement the instructions of the program ex pressed in binary or hexadecimal numb...

Page 125: ...of the form 110001102 followed by an 8 bit field representing the 8 bit immediate operand The equivalent machine language instruction for an ADD A 8 for example is the op code 110001102 or C6H followed by 000010002 or 08H The entire program representing the addition of one through ten could be loaded into the Z 80 microcomputer by means of a control panel if the microcomputer has one or monitor pr...

Page 126: ...ere to return When the B reg ister is decremented the Z flag is set if the result is zero and reset if the result is nonzero If the B register is nonzero 9 through 1 the JP NZ LOOP instruction will detect the nonzero NZ and jump back to LOOP If the B register holds a 0 the Z flag is set and the conditional jump back to LOOP will not be made causing the CPU to execute the next instruction HALT Manu...

Page 127: ...N FORM AT INSTRUCTION 0100H 1 AF 10101 111 XOR A 0101H 2 060A OD 000 110 00001010 LD B 10 0103H 1 80 10000 000 LOOP ADD A B 010414 1 05 00 000 101 DEC B 0105H 3 C20301 11 000 010 00000011 00000001 JP NZ LOOP 0108H 1 76 0111 0110 HALT 0109H Fig 9 2 Manual assembly process program 2 Although it is feasible to assemble long programs by manual methods it is extremely uneconomical There is too much of ...

Page 128: ...ermix comments with the symbolic form of the instruction 3 Automatic assembly of forward and backward references to symbolic locations 4 Automatic representation of various number bases 5 Expression evaluation 6 Pseudo operations or nongenerative assembler instructions that define locations equate symbols reserve memory and other convenient features ASSEMBLY FORMAT The mnemonic representation of i...

Page 129: ...g 9 3 Typical Z 80 assembly language format column describes the action of the instruction as was shown in Fig 9 2 The four columns make up an assembly language line In gen eral the length of assembly language lines has been determined by the length of lines on the input devices such as teletypewriters and punched card readers In actual practice as in the assemblers dis cussed in the manufacturers...

Page 130: ...ASK 1 120 1039 OF RRCA 121 103A OF RRCA 122 103B OF RRCA 123 103C OF RRCA ALIGN FOR CONVERSION 124 103D CD4710 CALL CVERT CONVERT 125 1040 3EOF LD A FH MASK 2 126 1042 Al AND C GET SECOND CHARACTER 127 1043 CD4710 CALL CVERT CONVERT 128 1046 C9 RET 129 130 1047 C630 CVERT ADD A 30H CONVERT TO 0 15 131 1049 FE10 CP 10 TEST FOR 0 9 Fig 9 4 Typical Z 80 listing messages indicating assembly errors suc...

Page 131: ...09H GREATR c 14AFH EQUAL The arrows represent instructions not defined The locations to the left represent the locations after assembly Most assemblers make two passes The first decodes the mnemonics constructs as much of the instruction as possible counts the bytes in the instruction and constructs a symbol table representing all labels and symbols in the program The second pass resolves all addr...

Page 132: ...nd literal data and in more sophisticated assemblers absolute and relocatable symbols Expression operators allow addition subtraction multiplication and in some cases divi sion and shifting The operators are usually represented by predict able symbols such as and for addition subtraction multiplication and division Elaborate expressions find little use in assembly language programs and in some cas...

Page 133: ...process The EQU pseudo op equates a label to another label or a numeric value The EQU is used for convenience in assigning recognizable names to constants or expressions An example of an EQU repre senting the length of a table is defined below Here represents the current assembler location the contents of the assembler loca tion counter Source Location Line 0100H TABLE O101H 0102H 0103H 0104H 0105...

Page 134: ... the as sembler location counter by the argument which represents the number of bytes to be reserved When the assembled object module is loaded by the loader program after assembly the block of storage allocated by the DEFS will not be affected and will retain the mean ingless data in the memory area before the load An alternative way to reserve storage is to use an ORG pseudo op Both of the state...

Page 135: ...er if a resident assembler is being used or into the host com puter if a cross assembler is employed The assembler will then read the source from the storage medium for the first pass If paper or magnetic tape cassettes are used as the storage medium the paper tape or cassette may then have to be repositioned manually to the start of the source image in other cases the system will automati cally r...

Page 136: ... The most sophisticated of the moves transfers up to 64 K bytes in one instruction 8 BIT MOVES The 8 bit load group allows data to be moved from a CPU register to memory or from memory to a CPU register in a variety of ad dressing modes Moving data to or from the A register is a special subset in this group The A register is given precedence because it is the primary register used for arithmetic l...

Page 137: ...to CPU registers or back again are 1 Using any CPU registers and HL as a pointer in register in direct mode 2 Using indexed addressing with any CPU registers 3 Using direct extended type addressing with the A register only 4 Using BC or DE register indirect addressing with the A register only We will discuss each of these methods in turn and illustrate 8 bit data movement to and from CPU registers...

Page 138: ...remented Although there are many other ways to implement this problem in the Z 80 programs written for the 8008 had to use this method to access random data as only the HL register pair was available as a pointer LD HL STORI LD HL A LD HL STOR2 LD HL B LD HL STOR3 LD HL C LD HL STOR4 LD HL D STOR1 DEFB 0 c STOR2 DEFB 0 c STOR3 DEFB 0 STOR1 ADDRESS STORE A STOR2 ADDRESS STORE B STOR3 ADDRESS STORE ...

Page 139: ...third byte of the instruction would be 4 0 4 and 8 respectively Here the process of storing data within the 256 byte block was made much more efficient than the example using the HL register pair pointer Or was it Let s compare the rel ative sizes and timing of the two programs The first program using the HL registers used four three byte instructions LD HL STORX and four 1 byte instructions LD HL...

Page 140: ...T LD IY B DEC IX DEC IY NXT3 LD B IX NEXT LD IY B Code such as the above is inefficient in memory storage because the same basic operation is repeated many times The transfers at NXT1 NXT2 and NXT3 are almost identical If 100 bytes were to be transferred it would of course be ludicrous to repeat the identi cal actions 100 times The most efficient way to implement repetitive actions is by looping b...

Page 141: ...LK2 4 BLK1 4 96 4 4 BLK2 5 BLK1 5 95 BYTE 5 5 1 1 r r BLK2 95 BLK1 95 4 BYTE 96 ITERATION 96 AFTER BLK2 96 BLK1 96 3 97 97 BLK2 97 BLK1 97 2 98 98 BLK2 98 BLK1 98 1 99 99 BLK2 99 BLK1 99 0 BYTE 100 100 Fig 10 2 Indexing example 8 BIT MOVES USING THE A REGISTER AND EXTENDED ADDRESSING The A register can be loaded or stored using extended address ing In this case the address specified is in the inst...

Page 142: ...R2 GET VAR2 FOR B LD B A LD A VAR1 GET VAR1 FOR A 8 BIT MOVES USING THE A REGISTER AND BC OR DE REGISTER INDIRECT The four instructions LD A DE LD A 13C LD DE A and LD BC A use BC or DE as pointers in a manner similar to the way HL is used as a pointer for the previously discussed moves Here again this addressing mode is very efficient as long as the data being accessed is contiguous data in a blo...

Page 143: ...ave specifically been set up for handling address related data If convenient though all instructions can be used to load and store nonaddress operands such as 16 bit double precision values or ASCII character data IMMEDIATE LOADS OF 16 BITS Many of the immediate loads have previously been illustrated in this chapter BC DE HL IX and IY are typically loaded with the starting address of data blocks c...

Page 144: ...SP IX IY or SP registers may be loaded from or stored to memory by instructions in this group As an example suppose that the BC DE and HL registers are to be loaded with the addresses of three blocks of memory but their contents are to be saved and restored for later use As an alternative to storage in the stack covered a little later in this chapter the three register pairs may be saved by LD SAV...

Page 145: ...le more overhead when only one register is to be saved in the stack for temporary storage In the Z 80 register pairs BC DE HL AF and registers IX and IY may be pushed and popped to the memory stack As each is pushed to the stack the data in the high order byte of the register pair is put into the top of stack 1 and the data in the low order byte is put into top of stack 2 The SP register is decrem...

Page 146: ...as in the following example which exchanges the BC and IY and DE and IX registers PUSH BC STACK NOW HAS BC PUSH IY STACK NOW HAS BC IY PUSH DE NOW BC IY DE PUSH IX NOW BC IY DE IX POP DE IX TO DE POP IX DE TO IX POP BC IY TO BC POP IY BC TO IY The stack register may also be used to facilitate processing of strings of data although care must be taken to maintain the stack pointer properly when this...

Page 147: ...e 1000 bytes of data at 10 microseconds per byte requires 10 milliseconds or 1 100 of a second Although the time required per byte in the Z 80 is about one third of this block movements still take large amounts of time in comparison to other program operations With the above proviso in mind let us see how the block transfer instructions in the Z 80 can be set up The first of these is the LDI instr...

Page 148: ...e bytes were 0 the move would stop The following code terminates the move if the next byte to be moved is zero The source byte about to be moved is first tested before the move occurs and if zero the move is terminated The OR A A instruction tests the zero nonzero status of the byte without affecting the byte The Z flag is reset if any bit in the byte is a one and set if all bits are zeros MOVE LD...

Page 149: ... I 4 If no processing is to take place between the transfer of individ ual bytes then the LDIR may be used The LDIR is set up in exactly the same manner as the LDI If N bytes are to be transferred how ever the LDIR will execute N times For each transfer the LDIR takes 5 25 microseconds the LDI takes 4 0 microseconds except for the last transfer BC 0 in which the LDIR takes 4 0 micro seconds LD HL ...

Page 150: ... them transfer data between the current set of CPU registers and the primed set Three others allow the HL and index registers to exchange their contents with the top of the stack The last simply exchanges the contents of DE with HL When the CPU is initialized one set of the two eight register sets becomes the current set The other set containing A F B C D E H and L may be accessed via the two exch...

Page 151: ... DE to HL for the limited arithmetic operations that can be performed to HL As an example of this suppose the contents of DE were to be doubled The following code would move DE to HL add HL to itself to double the contents and move the result back into DE EX DE HL DE TO HL ADD HL HL HL HL TO HL EX DE HL HL TO DE The remaining three instructions in this group exchange the con tents of the top of st...

Page 152: ...adds and subtracts by means of a special decimal adjust S BIT ARITHMETIC OPERATIONS In 8 bit arithmetic operations two 8 bit operands are added or subtracted One of the operands must be in the A register while the other operand may be an immediate operand an operand in an other CPU register or an operand from memory The result of the operation always goes to the A register The add or subtract func...

Page 153: ...ister pointed to BLK O after the last iteration of the loop and the checksum could be stored without further ad justment to the index register If the block of data were to be read in from the I O device and the checksum to be calculated and compared a subtract instruction could be used to advantage LD IX INBLK 1 SET PNTR TO START OF DATA LD A IX 1 GET CHECKSUM LD B 63 SET COUNT TO 63 LOOP SUB IX S...

Page 154: ...racters now 0 through 9 or a positive number for all ASCII characters greater than ASCII 39H decimal 9 A test at the JP causes a jump to the error routine if this limit check fails Finally the decimal equivalent of the ASCII character is restored by adding 10 to yield 0 9 for the converted character If an add or subtract results in an effective add of two 8 bit oper ands of similar signs overflow ...

Page 155: ...rom previous orders therefore an ADD or SUB is used Subsequent adds and subtracts utilize the ADC add with carry and SBC subtract with carry borrow instructions to propagate the carry or borrow ADD4 NE LD LD LD ADD LD LD ADC LD LD ADC LD LD ADC LD S IX OP1 3 IY OP2 3 A IX A IY IX A A IX 1 A IY 1 IX 1 A A IX 2 A IY 2 IX 2 A A IX 3 A IY 3 IX 3 A POINT TO LOW ORDER BYTE POINT TO LOW ORDER BYTE OPl OP...

Page 156: ...next subtract the carry will be set or reset depen dent on the last SBC instruction since no other instruction in the loop affects the carry After four subtracts from low to high order the count in B is 0 and the instruction at DONE is executed and the result is in OPl to OPl 3 8 BIT LOGICAL OPERATIONS The 8 bit logical operations are similar to the 8 bit adds in that the same addressing modes are...

Page 157: ...ata byte If one bed digit was in the A register in the form 0000JJJJ2 and the second was in the B register in the form KKKKO0002 a merged result of the form KKKKJJJJ2 could be obtained by OR B MERGE TWO BCD DIGITS As another example of the ORing function suppose that the high est order or most significant bit in a table of ten bytes was to be unconditionally set The following code would set the ms...

Page 158: ...ok at the following pro gram which finds the smallest number in a list of positive numbers As each new number is accessed it is compared with the previous smallest number If the new entry is smaller it replaces the previous smallest number in the B register When the last number in the list has been compared the B register holds the smallest number in the list The numbers in the list may range from...

Page 159: ... to cause a branch to DONE Next the index reg ister is incremented in preparation for the next comparison A com parison is then done of the current value to the smallest in B if the current value is smaller it replaces the contents of B A jump to NEXT is then made for the next comparison The above example is of a magnitude or unsigned comparison How is the signed comparison implemented There are f...

Page 160: ...6 BIT ARITHMETIC OPERATIONS Just as the A register was the main accumulator that was used for 8 bit arithmetic and logical operations the HL register is used as an accumulator for 16 bit arithmetic operations Register pairs BC DE HL and SP may be added to or subtracted from the contents of the HL register The add may be with or without carry but the subtract is always with borrow The Z 80 instruct...

Page 161: ...lf The obvious use for this is in indexing through tables or other data structures in memory where data is located every nth byte in the table If n is loaded into one of the register pairs the index register may easily be altered to index to the next location Let us see how this works The following pro gram searches a table of 128 entries for a given key value Each entry is seven bytes long and th...

Page 162: ...ment the register pair as these instructions do set the carry and in some cases the zero flag Here is an example of how the ADD HL SS instruction may be used to control the number of iterations through a LOOP LD DE 1 LOAD 1 TO DE LD IX TABLE START OF TABLE LD HL COUNT LOAD COUNT OF N 1 LOOP PROCESSING INC IX POINT TO NEXT BYTE OF TABLE ADD HL DE DECREMENT COUNT BY 1 JP C LOOP CONTINUE The count is...

Page 163: ...erations are convenient during normal processing in most programs DECIMAL ARITHMETIC OPERATONS When an 8 bit add or subtract is performed the arithmetic and logical unit in the Z 80 CPU performs a straight binary add or sub tract Some early computers performed bcd adds and subtracts BIT B HL 7 0 BYTE 0 1 1 0 0 1 0 1 1 THIS B 1 0 1 B 1 1 0 YTE FOR ALL THREE INSTRUCTIONS SET B HU THISFIELD FORALL TH...

Page 164: ...c ond example subtracts BCD2 from BCD1 stores results in BCD1 BCDADD LD A BCD2 1 GET LS BCD DIGITS OP2 LD B A LD A BCDI 1 GET LS BCD DIGITS OP2 ADD A B DAA BCD ADD LD BCD 1 1 A STORE LS RESULT LD A BCD2 GET MS BCD DIGITS OP2 LD B A LD A BCD1 GET MS BCD DIGITS OP1 ADC A B DAA BCD ADD LD BCD1 A STORE MS RESULT DONE c BCDSUB LD IX BCD1 1 POINT TO LS OP1 LD IY BCD2 1 POINT TO LS OP2 LD B 2 LOOP COUNT ...

Page 165: ...oriented instructions permit testing and storage of data on a bit basis either in CPU reg isters or memory LOGICAL SHIFTS Logical shifts are perhaps the simplest shifts to understand In a logical shift of eight bits there is no consideration of the sign The data is shifted right or left one bit at a time The data is not re circulated to the opposite end of the register or memory location as it is ...

Page 166: ...reset The effect of the SRL has been to divide by 2 while the SLA has multiplied by 2 For each bit position shifted right the SRL divides by 2 so that n SRLs divide by 211 For each bit position shifted left the SLA will multiply by 2 a shift of n bit positions divides by 2 As an example of this consider the routine below This routine finds the average of eight test scores where each test score rep...

Page 167: ...on or divi sion by 10 which can be factored into 8 2 The example below illustrates multiplication by 10 of an 8 bit number assumed to be 25 or less to fit with an unsigned 8 bit byte MUL10 LD A NUMBER GET MULTIPLICAND SLA A MULTIPLICAND X 2 LD SLA B A A SAVE MULTIPLICAND X 4 SLA A MULTIPLICAND X 8 ADD A B MLCND 8 2 M 10 Logical shifts are commonly used to align data within fields al though in some...

Page 168: ...with 16 bits MUL10 LD HL NUMBER GET MULTIPLICAND ADD HL HL 2 MULTIPLICAND PUSH HL POP DE TRANSFER TO DE ADD HL HL 4 MULTIPLICAND ADD HL HL 8 MULTIPLICAND ADD HL DE 10 MULTIPLICAND ROTATE TYPE SHIFTS The Z 80 has eight rotate type shifts some of which are redundant The rotates basically shift the eight bits of the operand and a carry or eight bits of the operand alone In the first case the shift is...

Page 169: ...UMP1 DEC B DECREMENT COUNT JR NZ LOOP GO IF NOT 8 BITS DONE A REGISTER NOW 0 IF EVEN OF 1 BITS 1 IF NOT The A register and carry are first cleared by the XOR Now the RL HL instruction is executed eight times At the end of eight times the contents of MEMOP are identical to the contents before the routine was entered The A register lsb was set or toggled each time a one bit was shifted around to bit...

Page 170: ... at UDGE two bit positions to the left in a logical shift The rotate may be used to propagate any carry along the 3 byte chain as follows SLUDGE EQU SHIFT LEFT UDGE UDGE IX 2 LD SLA IX 0 TO BIT 0 BIT 7 TO C RL IX 1 C TO BIT 0 BIT 7 TO C RL IX 2 C TO BIT 0 BIT 7 TO C SLA IX 0 TO BIT 0 BIT 7 TO C RL IX 1 C TO BIT 0 BIT 7 TO C RL IX 2 C TO BIT 0 BIT 7 TO C Another variation of this implementation use...

Page 171: ...10 Fig 12 3 SRA action AFTER SRA4 8 AFTER SRAS 4 The following routine performs an arithmetic right shift and saves the fractional part of the number in the B register If the binary point is considered to be between the two registers then the bit positions of the fractional portion represent 1 2 1 4 1 8 etc ARSSVF LD A NUMBER GET NUMBER LD B 0 CLEAR FRACTION SRA A N 2 RR B SAVE 1 8 SRA A N 4 RR B ...

Page 172: ... deals with 4 bit fields it is very convenient for processing bed data Each 4 bit shift brings in a new bed digit Let us see an example of the way the shifts may be used to manipu late bed data The program below converts ASCII characters assumed to be the digits 0 9 into bed digits Ten characters representing a 10 digit bcd value of 000000000010 999999999910 are stored in INBUF through INBUF 9 The...

Page 173: ...7 8 9 Fig 12 5 ASCII to bcd conversion As a further example of the use of the 4 bit rotates let us convert the opposite way going from packed bed digits in INBUF through INBUF 4 into ASCII characters representing the digits 0 through 9 Here we must go backwards through the buffer as we are filling two bytes of ASCII data with each packed byte of two bed digits IX will hold the address of the next ...

Page 174: ...O IF NOT DONE The only subtlety in the program above is that the A register must be cleared before each bed digit is shifted in as the shift does not affect bits 7 4 of the A register BIT SET RESET AND TEST GROUP The instructions in this group enable any of the eight bits in a CPU register or memory operand to be tested set or reset Register indirect or indexed addressing is permitted for addressi...

Page 175: ...te in memory the following code is used LD HL BYTE POINT TO BYTE BIT 7 HL TEST MS BIT JR Z ZERO GO IF BIT IS A ZERO ONE BIT IS A ONE To set a bit in a memory operand LD IX BYTE POINT TO BYTE SET 5 IX SET BIT 5 To reset a bit in a memory operand LD IY BYTE POINT TO BYTE RES 1 IY RESET BIT 1 Of course any of the three bit instructions may also be used to test set or reset any bit in a CPU register B...

Page 176: ...ata it is convenient to address the pixels by row column representation The pixel in the upper left hand corner is 0 0 row 0 column 0 the pixel in the upper right hand corner is 0 255 the pixel in the lower left is 255 0 and the pixel in the lower right corner is 255 255 The problem is to convert a pixel address from row column representation to the actual bit address and access the bit in VDTTB1 ...

Page 177: ...DER BITS CPL AND 7 GET BIT ADDRESS SLA A ALIGN BIT ADDRESS SLA A FOR BIT INSTRUCTION SLA A RET RETURN These routines are probably more sophisticated than any we have considered thus far In the first place they are true subroutines callable by a CALL instruction The return is made with the RTN instruction There are three entry points in the subroutine TESTPX which tests the value in a pixel SETPX w...

Page 178: ...bit is given by the remainder of COLUMN 8 GTADD calculates the byte displacement by shifting A and B and then calculates the actual address within the table by adding the displacement to the address of the start of the table The byte address is then stored in HL The bit address of the pixel is found by masking the three least significant bits of the column address in B Since these are the inverse ...

Page 179: ... SET B HL THREE INSTRUCTIONS THIS FIELD CHANGES 7 0 FOR INSTRUCTION BYTE 0 1 1 0 0 1 0 1 1 THIS FIELD COMPUTED 1 1 B 1 1 0 IN GTADD RES B HL 7 0 BYTE 0 1 1 0 0 1 0 1 1 1 0 B 1 1 0 Fig 12 9 Instruction modification for VDT bit routine The previous program utilizes many of the shifting bit manipula tion indexing and logical functions discussed in this and previous chapters It also introduces several...

Page 180: ... HL BC SUBTRACT DIVISOR JR NC DONE GO IF DONE INC DE BUMP QUOTIENT JP LOOP CONTINUE DONE The divisor is effectively subtracted from the dividend until the residue goes below 0 For each successful subtract the quotient is incremented by one The best case execution of this program is about 25 microseconds The worst case time is about 1 2 second With an average time of about a millisecond the program...

Page 181: ...T PARTIAL PRODUCT OUT B C 0 8 BIT MULTIPLICAND I BC ADDS TO H L Fig 12 10 An 8 bit multiply register arrangement The general form of division of the Z 80 and similar microproces sors is also related to the paper and pencil method In this case the restoring division of manual methods is used The residue or partial dividend is examined to see if the divisor will go into it is less than or equal to t...

Page 182: ...preset to a 1 in the lower end of the L register If the subtract will not go a restore is done ADD HL BC and the quotient bit reset to 0 At the end of the divide the residue or remainder is in H and an 8 bit quotient has been shifted into L Overflow is possible if the quotient cannot be resolved in eight bits The preceding is a brief introduction to implementations of un signed multiplies and divi...

Page 183: ...G String operations are important in text processing and compiler operation and some higher level languages have been implemented specifically to deal with string manipulation The Z 80 has the capability to search a sequence of data bytes for a given byte The search may be made for character or other data as the implementation is only concerned with finding a data byte that matches a search key Th...

Page 184: ... BYTES MAXIMUM CPIR SEARCH STRING FOR JP Z FOUND GO IF CHARACTER FOUND NOT FOUND FOUND DEC HL POINT TO LD PNTR HL SAVE POINTER TO The A register is loaded with the hexadecimal equivalent of an ASCII dollar sign Register pair HL is initialized with the address of the start of the character string STRING Since 64 characters are to be searched a byte count of 64 is loaded into BC The CPIR se quences ...

Page 185: ... average search time through a 64 character string 64 2 x 5 25 168 microseconds The corresponding code for an access compare conditional test adjust of byte count and pointer and conditional test would be about double the CPIR or CPDR and occupy a great deal more memory If a key of more than one character is required the compare string instructions may also be used but the comparison process will ...

Page 186: ...HAR OF KEY CP A D COMPARE JP NZ LOOP GO IF NOT FOUND FOUND HL POINTS TO MATCH 1 If the first key character has a match then the second level com parison at SECLVL is entered HL at this point points to the match plus one so that the next character can be picked up directly A is then loaded with the second key character and a comparison made If there is a compare FOUND is executed if there is no com...

Page 187: ...R CPIR SEARCH FOR 1ST CHAR JP NZ NFND GO IF NOT FOUND SECLVL PUSH HL SAVE POINTER POP IX POINT TO 2ND CHAR LD A IX ADD A IX 1 ADD A IX 2 ADD A IX 3 COMPUTE HASH CP D COMPARE TO KEY HASH JP NZ LOOP GO IF NO MATCH MAYBE LD IY CHAR 1 POINT TO 2ND CHAR OF KEY LD A IX CP A IY JP NZ LOOP GO IF NO MATCH 2ND CHAR LD A IX 1 CP A IY 1 JP NZ LOOP GO IF NO MATCH 3RD CHAR LD A IX 2 CP A IY 2 JP NZ LOOP GO IF N...

Page 188: ...ts of one ASCII character A table is TABLE TABLE 12810 TABLE 256 TABLE 384 Fig 13 2 Employee table format TABLE 2560 0 ENTRY 1 2 3 4 LAST NAME 14 15 FIRST NAME 24 25 OTHER J DATA 127 01 ID made up of a number of entries that may be any number of bits long and may contain subgroupings of data Within the table entries may be ordered in random order or indexed by some external key Ordering may be don...

Page 189: ...ve the data into the print buffer Suppose that the entries in the above example were not in any order or not indexed by ID number If the ID was 1 255 then a search through the table could be made for a given ID key by using the CPI or CPD instruction The ID is located in the last byte of each 128 byte entry in the table see Fig 13 2 Searching for the ID from end of the table back would proceed as ...

Page 190: ...e following routines the general parameters are TABLE the starting address of the table NENT the number of entries in the table and LENT the length in bytes of each entry The address of the last word in the table 1 is given by LASTW The inputs to the multiply routine are in the A register multipli cand and B register multiplier The output of the multiplier rou tine is a 16 bit product in the BC re...

Page 191: ...be put into DE The number of bytes to move is then given by LASTW HL LENT and this value is computed and put into BC The source address is provided by HL LENT this is computed and loaded into HL for the LDIR The actions of this move are shown in Fig 13 3 AFTER DELETE TABLE 2 LENT OF BYTES PER ENTRY TABLE N ENTRY 1 ENTRY TO DELETE NEW LOCATION NOT USED ENTRY N Fig 13 3 Delete table entry actions Th...

Page 192: ... at END and is not shown If a greater than value is found then the pointer value in HL minus one defines the source starting ad dress for the move The destination address is the length of one entry plus the source starting address The number of bytes to be moved is the total number of table entries minus the current entry multiplied by the number of bytes per entry The move must be a LDR to preven...

Page 193: ...rch algorithms are possible for ordered data entries A binary search accesses table entries by comparing the sense of the key table entry comparison In a table ordered with entries in ascend ing order the next entry accessed will be the middle entry of the remaining entries before the current entry if the current entry is greater than the key value or the middle entry of the remaining entries afte...

Page 194: ...RY LT KEY LD B E CURRENT TO LOW JP LOOP CONTINUE JUMP3 LD C E CURRENT TO HIGH JP LOOP CONTINUE The routine first of all compares the last entry of the table with the search key to avoid truncation errors in computing the next in dex If the key is not found the iterative portion of the routine is entered For each iteration new low and high limits are established based on the results of the last com...

Page 195: ...ied the overhead of altering data tables becomes significantly large A list is a data structure that reduces the over head by eliminating movements of large blocks of data when items are changed within the list A single ended list consists of entries that are noncontiguous in memory Each entry consists of the data as sociated with that list entry and a pointer address to the next data items in the...

Page 196: ...em The address of the new data item is loaded with the link address of the data item before the insertion point These actions are illustrated in Fig 13 9 The following Z 80 code shows a search of a single ended linked list for a given search key value Each data item of the list consists of an 8 bit data value and a 2 byte link address INSERT LD HL HEADLS HEAD OF LIST LD A KEY SEARCH KEY LD BC 1 FO...

Page 197: ...e ADC HL SS and SBC HL SS are unique in that they set the Z flag if the result is zero none of the other 16 bit arithmetic instructions affect the Z flag If the address is a valid address the data value from the next list entry is retrieved and a match is tried If no match is found the link address of the data item is loaded into HL in preparation for the next comparison List operations for insert...

Page 198: ...s picked up in BC This link address will point to the list entry which will be immedi ately after the inserted entry The address of the new data item is in the 2 byte location NEWLKA and NEWLKA 1 This address is stored in the link address bytes of the previous list entry Finally the link address of the list entry which will precede the inserted entry is stored in bytes one and two of the insert en...

Page 199: ... that occur in one place in memory These segments can be used by many different parts of the program avoiding duplication of the code at every point where the functions of the subroutine are to be performed Each subroutine is entered by a CALL which saves the return address of the instruction following the CALL in the stack each subroutine is terminated by an RET or return Returns may be condition...

Page 200: ...ics may be replaced with more descriptive mnemonics such as V or NV for overflow and no overflow and P and NP for parity or no parity Table 14 1 Conditional Jumps Flag Extended Form Relative Form NZ nonzero JP NZ LOCN JR Z LOCN Z zero JP Z LOCN JR NZ LOCN NC no carry JP NC LOCN JR C LOCN C carry JP C LOCN JR NC LOCN PO parity odd JP PO LOCN none PE parity even JP PE LOCN none P sign positive JP P ...

Page 201: ... word example word is from 0 through 11 The following code takes the mode word and jumps out based on a jump or branch table to the proper processing routine for the current system mode TESTMD LD BC JUMPTB JUMP TABLE ADDRESS LD A MODE GET MODE WORD AND A FH STRIP OFF MODE BITS LD L A LD H 0 MODE TO BC ADD HL HL MODE 2 ADD HL BC JUMPTB MODE 2 JP HL JUMP OUT JUMPTB JR MODEO JR MODE JR MODE2 JR MODE3...

Page 202: ...s executed This instruction replaces the code DEC B DECREMENT COUNT IN B JR NZ LOOP GO IF NOT AT END In any case where an iterative routine is implemented with a loop count of 256 or less the DJNZ may be used to advantage Using one of the previous examples as an illustration here is a typical use of DJNZ PARITY XOR A CLEAR PARITY AND C LD B 8 INITIALIZE COUNT LD HL MEMOP MEMORY OPERAND ADDRESS LOO...

Page 203: ...the code below which shifts the DE register pair one bit posi tion to the right in a logical shift SHRL SRL D RR E RET SHIFT HIGH ORDER SHIFT LOW ORDER RETURN TO CALLING PROGRAM In many cases however subroutines will perform a function that requires a parameter or number of parameters defining the function A simple example of this would be the more functional subroutine that follows which shifts t...

Page 204: ...gits in a specified buffer area The parameters to be passed are defined in a calling sequence that is nothing more than a description of the parameters used in the subroutine how they are passed and how the subroutine is used Many times it is convenient to define the calling sequence in the assembly code itself as follows SUBROUTINE BXOAS FUNCTION THIS SR CONVERTS A 16 BIT BINARY NUMBER IN D E TO ...

Page 205: ... a pop for every push All of the above examples have dealt with unconditional CALLS and RETurns but conditional calls and returns may also be made The conditions and mnemonics for these are the same as for the con ditional extended jumps as shown in Table 14 2 The uses of the conditional calls and returns are identical to the applications of their unconditional counterparts In the following exampl...

Page 206: ...ETURN WITH C Z P SET The RST or restart instruction is rather a leftover from the 8080 implemented for compatibility The NMI and mode 1 interrupt capability serves small microcomputer configurations well and the mode 2 interrupt capability is excellent for larger configurations with many interrupts of different levels If the RST is not to be used in external interrupt circuitry mode 0 then it may ...

Page 207: ...are typical of the commonly used routines that could be placed in page 0 The call is made to the proper page 0 location by the RST with an argument previously equated to the page 0 location RST LDINC would be identical to RST 0 for example REENTRANCY The subroutine calls returns and stack instructions facilitate the writing of reentrant code Reentrancy in a portion of code means that the code may ...

Page 208: ...ue stored for the second entry of FINDIT not the first Reentrancy has destroyed the previous contents of TEMPI REENTRY FINDIT NTERRUPT LD LD LD ADD LD TEMP 1 A A HL B IX 30H A B HL A SAVE A TEMP GT NXT PARAM GT 2ND VALU STORE RESULT ENTER HERE BACKHR LD A TEMP1 RESTORE AFTER INTERRUPT PROCESSING ET ETURN TEMPI DEFS 1 TMPRYSTRG TEMP2 DEFS 1 There are many ways around reentrancy The easiest is to ne...

Page 209: ...USER 2 IN BC LD B 0 LD HL BUFTB TABLE OF BUFFER ADDRESSES ADD HL BC LD E HL INC HL LD D HL GET BUFFER ADDRESS CALL READK READ KEYBOARD JP Z OUT GO IF NONE AVAILABLE LD HL A STORE CHARACTER BUFTB DEFW BUFFO TABLE OF BUFFER DEFW BUFF1 ADDRESSES USERS DEFW BUFF2 0 THRU 4 DEFW BUFF3 DEFW BUFF4 Other ways to avoid the reentrancy problem are lock outs of subroutines in use disabling of interrupts during...

Page 210: ...ctions The interrupt actions in the Z 80 are controlled by the interrupt enable disable instructions and by the interrupt mode instructions Several interrupt modes are possible depending on system configu ration The maximum interrupt capability of a Z 80 system will han dle many levels of interrupts with priority encoding and automatic vectoring A REGISTER I O INSTRUCTIONS The IN A N and OUT N A 1...

Page 211: ...t also be able to decode the query for ready status and the request to transmit the data byte A simple way to implement the preceding instruction is to assign one I O address to the status query port and one to the I O data port Some format for the status must also be established so that the CPU can decode the status in software Assuming that a Teletype keyboard is being read with a status port ad...

Page 212: ...ent to the program being executed DMA operations are described later in this chapter The OUT N A instruction functions quite similarly to the IN A N instruction The output process proceeds as follows The ready status of the device controller is first tested by reading in the status If the device controller is ready done processing the previ ous character the program performs an OUT N A outputting ...

Page 213: ...ster must be loaded with the I O device address The contents of the C register is output to address lines A7 through AO while the contents of the B register are output to address lines A15 through A8 The B register contents may be used for communication of status or for outputting the current byte count as in the I O block transfer instructions to be discussed They may of course also be ignored as...

Page 214: ...r is initialized with an I O ad dress as in the case of an IN R C instruction As the INI is exe cuted the input data is stored into the memory location pointed to by the HL register After the data is stored the HL register pair is incremented by one and a byte count in the BC register pair is dec remented by one The Z flag is set if the contents of the BC register pair equals zero after instructio...

Page 215: ...NIR has no capability to test device controller status there is no built in handshaking logic The ques tion arises then of how the CPU is informed when the next data byte is available The answer is that it is not informed The I O device controller must be fast enough to transfer data at a 200 kb sec rate or must insert I O wait states to effectively make the INIR in struction time equal to the dat...

Page 216: ... JP NZ STATUS LOOP IF NOT 100 BYTES DONE RET RETURN The OTIR is an automatic output instruction analogous to the INIR From 1 to 256 bytes will be output from the specified block in memory according to the byte count in the C register The same im plementation as the INIR applies If the device is slow compared to the 190 000 byte per second rate of the OTIR I O wait states must be employed to match ...

Page 217: ...bility for the simple I O devices most large software systems include a software I O driver subroutine for each kind of I O device in the system The I O driver handles all communication with the device type and acts as a software interface between portions of the system programs that require I O service and the I O devices To illustrate this concept assume that several floppy discs are con nected ...

Page 218: ...and 4 and the number of bytes to be transferred is in bytes 5 and 6 The starting track and sector are in bytes 1 and 0 with the drive number 0 3 in bits 7 and 6 of byte 0 The status after the read or write is loaded after the read or write operation The type of completion is a 0 if no error occurred or a 1 if an error occurred with further status available to define the error in byte 7 For a posit...

Page 219: ...led as many of them change depending on the type of I O call The implementation of the I O driver DISCD is not shown be cause it is strictly dependent on the type of floppy disc drive and the interface design There will be quite a bit of latitude in how the actual interface is implemented Perhaps the 8080 type interrupt mode 0 will be implemented instead of the mode 2 table vectored interrupts Pos...

Page 220: ...d sequence to I O port 30H I O port 30H is the address of the floppy disc controller DMA control registers When the controller receives the start DMA setup command it expects that the next 4 bytes output to port 30H will be the two bytes de fining the address for the DMA and the two bytes defining the num ber of bytes to transfer After receiving the fourth byte DMA action starts immediately Here a...

Page 221: ...sually unique for every kind of interrupt In the interrupt processing routine the first order of business is to ascertain that other interrupts are disabled until the contents of all registers and flags that will be used in the interrupt routine can be saved All maskable interrupts are disabled on an interrupt until the issuance of the next EI instruction so the following sequence can be executed ...

Page 222: ... during their execution The El instruction prevents an inter rupt from occurring until one instruction after the EI allowing suc cessful completion of the RETI instruction to effect the return from interrupt As the maskable interrupt NMI can occur at any time it may occur at a time when maskable interrupts are disabled and registers are being saved or restored or lock out conditions for reentrancy...

Page 223: ...mented again and again and could be made part of a permanent library of routines that may be called on as required Each subroutine discussed here is considered from the standpoint of a separate functional module rather than in line code System design may utilize precanned mod ules such as these with overall system functional requirements in a combination of top down system requirements and bottom ...

Page 224: ... B RTN The actual code within the subroutine would be an expansion of that in Chapter 11 CMPARE CP B A B EX SP HL GET RETURN JR Z EQUAL GO IF A B PUSH AF SAVE A FLAGS XOR B JP P SAME GO IF SIGNS EQUAL POP AF RESTORE A FLAGS TEST JP C LESST A B JP GREAT A B SAME POP AF CCF JP TEST GREAT INC HL BUMP TO CALL 4 INC HL EQUAL INC HL BUMP TO CALL 2 INC HL LESST EX SP HL RESTORE RTN RET RETURN The compari...

Page 225: ...ned by the B register input value so that DELAY B x 0 1 sec approximately The maximum delay is 25 6 seconds with B 256 but longer delays can be implemented by altering the initialization value of HL MULTIPLY AND DIVIDE SUBROUTINES An 8 bit by 8 bit unsigned multiply was discussed in Chapter 12 The operands in this multiply are somewhat limited for many appli cations A 16 bit by 16 bit multiply wou...

Page 226: ...s was the case of the 8 by 8 multiply the operands are somewhat too small to be practical in many cases A 32 bit by 16 bit unsigned divide is shown next that will cover divides in which the quotient can be resolved in 16 bits The 32 bit dividend is input in H L D and E while the 16 bit divisor is in register pair BC DVDE16 LD A 16 ITERATION COUNTER LOOP ADD HL HL SHIFT HL LEFT EX DE HL DE TO HL FO...

Page 227: ...number of bytes of precision is con tained in C The carry is set on return to reflect the last most sig nificant add MPADD LD B 0 NOW HAVE N IN BC ADD HL BC POINT TO LS BYTE 1 DEC HL POINT TO LS BYTE EX DE HL ADD HL BC LS BYTE 1 DEC HL LS BYTE EX DE HL SOURCE POINTER IN DE OR A CLEAR CARRY LOOP LD A DE GET BYTE ADC A HL SOURCE DEST CARRY LD HL A STORE RESULT DEC HL DECREMENT DEST PNTR DEC DE DECRE...

Page 228: ... two at a time as two hex digits may be held in eight bits ASCII bcd characters will be con verted two at a time for the same reason When the data represents ASCII decimal digits the question becomes one of a convenient length for conversion Eight bits will hold the decimal values of 0 to 255 and sixteen bits will hold up to 65 536 Neither range lends itself to consecutive conversions of strings o...

Page 229: ... A 10 CHECK FOR A F JP M JUMP1 GO IF 0 9 SUB A 7 CONVERT A F TO 0 15 JUMP1 ADD A C MERGE RESULT RET RETURN The bed conversion routine in this set converts two ASCII charac ters assumed to be the ASCII bed digits 0 9 to an 8 bit value in the A register representing two bed digits As before HL points to the first character of the string on input and the third character of the string on output ASXBCD...

Page 230: ...TO ASCII CONVERSIONS The conversions in this group operate in reverse from the ASCII to base conversions of the previous subroutines Here a binary value is converted to ASCII binary hexadecimal bcd or decimal charac ters On entry a pointer to the buffer area is used to store the ASCII result on exit the pointer points to the next available storage byte in the buffer The next routine converts an 8 ...

Page 231: ...ond routine of this group converts an 8 bit binary value in the C register to two ASCII hexadecimal digits On entry HL points to the buffer area and on exit HL points to buffer 2 BXASH LD A FOH MASK AND A C GET FIRST CHARACTER RRCA RRCA RRCA RRCA ALIGN FOR CONVERT CALL CVERT CONVERT LD A FH MASK AND A C GET SECOND CHARACTER CALL CVERT CONVERT RET RETURN CVERT ADD A 30H CONVERT TO 0 15 CP A 10 JP M...

Page 232: ...fer 5 To avoid a 16 by 8 divide with a remainder use is made of a table lookup to find powers of ten The table consists of 104 103 102 101 and units and is indexed by the current iteration count of the loop A successive subtraction of the power of ten is performed to find the number of times each of the powers of ten will go into the residue The number of times each can successfully be subtracted ...

Page 233: ...L UTPUT BUFFERR FILLED WITH 2 ASCII DECIMAL CHARACTERS IHLI HL O 16 BIT BINARY H L OUTPUT BUFFER FILLED WITH 5 ASCII DECIMAL CHARACTERS Fig 16 2 Base X to ASCII conversions 11X FILL DATA ROUTINE The following routine fills a block of memory with a specified 8 bit binary value This routine is useful in zeroing tables or for filling a known data value into buffers such as all blanks to initialize a ...

Page 234: ...ons are of 8 bit unsigned values COMSTR LD A DE GET BYTE OF STRING SUB HL A B RET NZ GO IF NOT EQUAL INC DE BUMP A PNTR INC HL BUMP B PNTR DJNZ COMSTR CONTINUE IF NOT AT END RET RETURN TABLE SEARCH ROUTINE The following subroutine is a general purpose routine for search ing a table of n entries where each entry is made up of m bytes The key for the search is eight bits and the search value for eac...

Page 235: ...es remaining in the table The reentry address is a second entry point in the routine The initial entry is at SRTAB while the reentry point is at SRTAB1 SRTAB LD D 0 NOW HAVE BYTES ENTRY IN D E LOOP CP A IX COMPARE SEARCH KEY TO ENTRY RET Z GO IF MATCH SRTABI ADD IX DE BUMP IX TO NEXT ENTRY DJNZ LOOP GO IF NOT LAST ENTRY LD IX 1 FLAG FOR NOT FOUND RET RETURN 244 ...

Page 236: ...SECTION III Z 80 Microcomputers ...

Page 237: ......

Page 238: ...es and floppy discs to make up the microcomputer configurations desired Z 80 MCBTM MICROCOMPUTER BOARD The Z 80 MCBTM is a complete 7 7 x 7 75 inch single board com puter shown in Fig 17 1 A block diagram of the MCB is shown in Fig 17 2 The heart of the MCB of course is the Z 80 microproces sor chip RAM memory consists of 4K of dynamic RAM on the MCB board Up to 4K of EPROM PROM or ROM may be used...

Page 239: ...rol lines and a 122 pin connector is used to provide interfacing to other logic in the system or compatible MCB modules External power supply requirements are 5 VDC at 10 watts maximum MCB MEMORY The nominal memory mapping for the MCB is shown in Fig 17 3 The 4K bytes of EPROM PROM or ROM are normally located in block 0 memory locations 0000H to OFFFH with the 4K bytes of RAM in block 1 1000H to 1...

Page 240: ...hip 4K x 1 configuration At least part of the possible 4K bytes of ROM in the MCB will probably be one of the versions of the Zilog monitor The remaining area available for read only memory can OOOOH OFFFH 1O00H 1FFFH 2000 H Fig 17 3 Z 80 MCBTM nominal memory mapping FFFFH 4 K BYTES PROM ROM EPROM 4 K BYTES RAM 56K BYTES I UNUSED be used for EPROM erasable programmable read only memory or ROM read...

Page 241: ...sfers with full handshaking and interrupt capability as discussed in Chapter 8 The I O ports of the PIO connect directly to a set of wire wrap pins that can be connected to four 16 pin IC sockets on the MCB board Appropriate drivers can be provided in the sockets for external I O equipment and wire wrapped connections can be easily made to edge connector pins MCB SERIAL I O Serial I O is provided ...

Page 242: ...sion will suffice This configuration offers a complete program development system as a teletypewriter offers keyboard input and output and if the Teletype ASR 33 is em ployed paper tape input and output Programs may be developed and debugged with this system and saved on paper tape Note that assembly language capability is not provided and that assembly language programs such as a time sharing ser...

Page 243: ...nine standard modules A complete microcomputer system the Z 80 MCSTM is also avail able from Zilog The MCS uses the MCB and MDC and provides dual floppy discs power supplies card cage and chassis MCB MONITOR A description of the 1K version of the Z 80 MCB PROMT M moni tor is provided below The word monitor as applied to microcom puter systems essentially means debugging program in the smaller vers...

Page 244: ... 2 3 4 etc into the locations from 0300H the user would type SET 300 1 2 3 4 5 6 7 8 9 10 CR REGISTER displays the contents of a given register The user types in the command REGISTER followed by a one or two letter mnemonic signifying the register to be displayed Valid reg ister mnemonics are A B C D E F H L I A B C D E F H L IX IY PC or SP The mnemonic is followed by a blank rather than a carriag...

Page 245: ...This is helpful in breakpointing iterative code as it eliminates a breakpoint at each repetitions of an instruction To set a breakpoint at location 10AAH after 123H times through a loop the following command would be entered BREAK IOAA 123 C The JUMP command causes the monitor to jump to the specified address If previous breakpoint was entered all registers are restored to their contents before th...

Page 246: ...system in cludes a Z 80 CPU with 4K bytes of ROM 16K bytes of RAM expanded to 60K bytes and two floppy disc drives with a con troller A teletypewriter or other terminal may be connected to the system by the RS 232 or current loop serial interface included in the system A programmable hardware breakpoint module allows hard ware breakpointing on specified control signals and or addressing and data b...

Page 247: ...y is dedicated to the user s soft ware the user has control over system peripherals and CPU In the Monitor Mode this memory serves as main memory for editing and assembling The Real Time Storage Module Board contains a 256 by 32 storage array The storage array essentially stores events in the array as they occur on a rolling basis The user may specify the kind of events to be recorded under contro...

Page 248: ...e main tenance from disc storage OS Z 80 is resident in the read only mem ory of the Processor Module The debug software of the system is also resident in read only memory and contains commands similar to the MCB debug com mands In addition there are commands related to the Hardware Breakpoint Module and the Real Time Storage Module these com mands specify the breakpoint and storage conditions and...

Page 249: ...ation about the current files or disc may be listed on the system printing device OTHER ZILOG PRODUCTS In addition to the MCB modules and Z 80 Development System Zilog offers a Z 80 Simulator program and Macro Cross Assembler for use on time sharing services or larger computer systems The Simulator will execute Z 80 programs by interpreting Z 80 instruc tions while running in a host computer The M...

Page 250: ...er or OEM Original Equipment Man ufacturer they also are being offered to the computer hobbyist As a result many of the system components are available as kits in addi tion to fully assembled modules Many of the recent hobbyist kit manufacturers have produced products that have not come up to commercial standards in design production documentation or sup port The four manufacturers discussed here ...

Page 251: ...l purpose I O interfaces Fortunately the Digital Group offers a wide variety of modules for their bus and this disadvantage is somewhat alleviated The fourth manufacturer Radio Shack offers a turnkey micro computer system available to the computer hobbyist or small busi ness user only in assembled form The bus of course is not an S 100 bus although an interface between the Radio Shack system and 5...

Page 252: ...ixed at 2 MHz by a crystal oscillator the other is frequency variable by means of a small potentiometer The frequency of the second clock can be adjusted from about 1 MHz to 4 MHz if the second clock is selected Either of the two clocks or an external clock may be selected for Z 80 timing but the system clock the bus clock is always the 2 MHz output Courtesy Technical Design Labs Inc Fig 18 1 TDL ...

Page 253: ...voltages required for the Z16 are 5 VDC and 12 VDC and are available on the S 100 bus Courtesy Technical Design Labs Inc Fig 18 2 TDL Z 16TM board The Z16 board has several unique features One of these is a memory protect capability which will prevent selected 1 to 4K segments of the 16K board from being accessed for a write The memory protect is switch selectable A battery backup capability is pr...

Page 254: ... O ports are available They can provide serial I O at 110 to 9600 baud and interface to either a 20 mA cur rent loop or RS 232 device Baud rates of 110 Teletype 300 600 1200 4800 and 9600 are jumper selectable One parallel I O port is available to the user and can be software configured to either an input or output port Courtesy Technical Design Labs Inc Fig 18 3 TDL SMBTM board A second parallel ...

Page 255: ...0 debug and file commands In addition the monitor contains I O routines for standard system devices or user defined user written 1 0 de vices All I O in the other utility software is done via the I O drivers in the ZAPPLETM monitor The ZAPPLETM text editor is both a line oriented and character oriented text editor that allows the user to edit text files Lines may be inserted or deleted Character s...

Page 256: ...ts or compressions of them are interpreted and executed at run time rather than producing an executable output module at compi lation time The 8K BASIC is very complete and has such features as a trace function to display line numbers as the lines are executed and a listing of program variables The 12K SUPER BASIC is an expanded BASIC with many editing and formatting commands ap pended to the basi...

Page 257: ...a Z 80 function this time to indicate whether the clock is set at 2 MHz or 4 MHz Another feature of the CPU board is an on board WAIT state generator The WAIT state for the S 100 bus is identical in function to the WAIT state in the Z 80 it allows slow memory or I O de vices to send a WAIT signal to the CPU to provide extra time to respond to the CPU A jumper selectable WAIT state option on the CP...

Page 258: ... 4K byte and 16K byte RAM boards The 4K RAM is a static RAM while the 16K RAM is dynamic with a transparent to the user s program refresh Both the 4K and 16K RAM boards have a bank select feature which permits memory expansion to eight banks of 64K bytes In addition to the RAM memory Cromemco offers two types of PROM boards A 16K PROM board holds sixteen 1K byte 2708 EPROMs when fully popu lated T...

Page 259: ...r Z 2 to interface to a variety of control applications including real time process control Conversions are 5 5 µs which are quite fast for a card of this kind Other Cromemco hardware are the TV DAZZLERTM which pro vides color graphics capability using an ordinary television wire wrap boards extender cards and a joystick console for analog control inputs CROMEMCO Z 1 AND Z 2 MICROCOMPUTER SYSTEMS ...

Page 260: ...boards include a parallel I O board 8K static RAM TV Readout and Audio Cassette Interfaces 4K EPROM memory board and a Color Graphics Board Peripheral equipment is gen erally housed in cabinets that match the other system cabinetry in styling and color Keyboards tv monitors cassette drives and a matrix printer are available As with the other Z 80 microcomputer manufacturers combinations of the var...

Page 261: ...both upper and lower case alphabets numbers extended math symbols and Greek alphabet The cursor may be positioned forward and backward under software control Output of the tv section of the board is to a standard monitor Digital Group or others or to a standard television with input to the video section The Audio Cassette portion of the board records or reads data on standard Phillips type audio c...

Page 262: ...alone cassette interface prototyping boards and extenders and miscellaneous hardware DIGITAL GROUP SYSTEMS Various system combinations are offered by The Digital Group ranging from a four board Z 80 system with 10K of RAM I O boards and TV Readout Audio Cassette Interface to a hard copy system with Z 80 CPU TV Readout Audio Cassette Interface two I O Boards 18K of RAM Cassette Drive Interface with...

Page 263: ...bset of BASIC TINY BASIC and MAXI BASIC are available as higher level interpretive packages MAXI BASIC for the Z 80 provides bcd floating point arithmetic formatted output multiple statements per line and multiple line functions Arrays may be any number of dimensions and string manipulation is provided MAXI BASIC requires 8K of memory and the recommended system configuration is 18K The Z 80 Assemb...

Page 264: ...system The basic TRS 80 system may be expanded with up to 62K bytes of additional memory Within the keyboard case up to 12K of ROM and 16K of RAM may be added An expansion module is option ally provided for memory above these limits Although the system includes all cabling and connections for the video display and cassette recorder additional I O devices may be added by means of a 40 pin external ...

Page 265: ...s point x y RESET x y turns point x u off and POINT x y determines the state of the point CLS clears the screen Direct cursor control is provided with the PRINT AT x command The 4K version of BASIC will be supplemented by a 12K version Other software such as editors assemblers and disc operating sys tems are planned In addition a wide range of applications software such as game programs and busine...

Page 266: ...APPENDIX A Z 80 Electrical Specifications Z 80 electrical specifications Z 80 CPU ac characteristics and ac timing diagram are provided in the tables and figures on the follow ing pages 275 ...

Page 267: ...I x 11 c o V o O m O O O O O O O O O N 1 1 7 Cl O C O O N N I I 0 0 a 0 0 0 0 c c a d S c ID 0 u d rn rn m c m Y m Y 0 y p O v m m u 0 Ill r CL m O V u s S O O S 3 L O Y 0 7 a 3 o 0 o 0 a O O J J a T m Y Y N N N m O O d a Q u u E E O O a E r t o 0 X o x x x ...

Page 268: ...Test Conditions C a Clock Capacitance 20 pF d Pins U CIN Input Capacitance 5 PF nmeasure Returned to Ground LOUT Output Capacitance 10 pF VCC Fig A 1 Clock driver I TTL An external clock pull up resistor of 33012 will meet both ac and dc clock requirements 277 ...

Page 269: ...Y o v u u o E l w U d 2 0 0 0 U m 0 o I a o 0 0 E rn 3 J I3 I u 4 v E rn 0 C I IO 3 m w g I W W d o 0 o E o 0 0 c c m 3 0 w o o E E c c 0 oI3 LL LL s O O LL o o o d d LL LL o o w O O o 0 E E E W W O O O d K c w m o d 6 E E E d a LL E LL LL LL O m m O D j m m m m 1 m m m s t O a C D D O O In N IA N O d ar d j m O W a W O O a a _ H H T o F O V V N in M I 00033 J O a YYYY U V V T o N 0 T 1 N z i2 1 T...

Page 270: ... W W m W t J w w m a O m 6 O m m w w C C 0 w 0 C m W W w W W W U W w LL l O o m C n IQ O c N m m m m m c c LL E c N LL m e m e c c 3 J 2 K LL O CI Q N o o E E E 0 0 0 0 i i o LL i a s E E E 0 I F o o LL E E E 1 E E 2 2 E W Z LL o LL LL LL LL O O O O 2 2 2 O O LL LL N E F L O_ 7 T T 1p O o d T T T T m ip m LL LL LL LL LL LL LL C LL LL T T Q m N iE N _ 7 LL N 0 W 0 W T T T T m m W W 7 N W O O N W D ...

Page 271: ...I c v N O p O E c O t Q c O O 3 V v w c o l C O T I o M o_O w I I I I l I I v 9 v I LLg o F o x o o o E o Q _0 0 a I II II I N H o I II 3 m t II II 11 II 11 II II la Iz m II o alw o I d 4 E E_ X X I I w 3 0 W t r r t r t r W r Y __ _ C j F v N 1p Q F OH N u u O u P O R N z N M 7 280 ...

Page 272: ...0 5V TW LI TDIADI TS IDI _ _ _ TH TDIDI TH TS4V D DLIMII TDHIMII z 11 11 TDLIRFI I H kFl l FtC l I I i T DL MRI 7 MREQ TACM TDL RD RD WR IORQ RD WR WAIT HALT INT NMI BUSRQ BUSAK RESET M TDH bIMRI TDHO RD TDLI IR TD4 IR 1 TW NMLI TS RS I ITH TDH b IRD TDL IWRI TSIBQI Fig A 3 Z 80 ac timing diagram TDHif MRI DL BA FIADI TF D TCAF TCA CDF THI MRI DH bIWRI DH4 IR DHq RD DH DIWRI TDHIBAI 281 ...

Page 273: ...MP M CP HL JPO JP PO NN RP RET P CMP r CP R JZ JP Z NN RPE RET PE CNC CALL NC NN LDA LD A NN RPO RET PO CNZ CALL NZ NN LDAX B LD A BC RRC RRCA CP CALL P NN LDAX D LD A DE RST RST P CP E CALL PE NN LHLD LD HL NN RZ RET Z CPI CP N LXI B LD BC NN SBB M SBC A HL CPO CALL PO NN LXI D LD DE NN SBB r SBC A R CZ CALL Z NN LXI H LD HL NN SBI SBC A N DAA DAA LXI SP LD SP NN SHLD LD NN HL DAD B ADD HL BC MVI...

Page 274: ...APPENDIX C Z 80 Instructions Instructions for the Z 80 Microcomputer are presented in Tables C 1 through C 11 on the following pages 283 ...

Page 275: ... n IX d n 11 Oil 101 4 5 19 00 110 110 d LD IY d n IY d n n 11 Ill 101 4 5 19 00 110 110 it LD A BC A BC 00 001 010 1 2 7 LD A DE A DE 00 Oil 010 1 2 7 LD A nn A nn 00 Ill 010 n 3 4 13 LD BC A BC A u 00 000 010 1 2 7 LD DE A DE A 00 010 010 1 2 7 LD nn A nn A 00 110 010 n 3 4 13 LDA I A I I IFFI 0 0 II 101 101 2 2 9 01 010 Ill LDA R A R t IFFI 0 0 II 101 101 2 2 9 01 Oil ill LDI A I A A II 101 101...

Page 276: ...LD nn IY nn I IYH 11 1l l 101 4 6 20 nn IYL 00 100 010 LD SPHL SP HL 11 111 001 1 1 6 LD SP IX SP IX I 1 0ll 101 2 2 10 II 111 001 LD SP IY SP IY II 111 101 2 2 10 11 Ill 001 qq Patr PUSH qq SP 2 qqL 11 qqO 101 1 3 11 00 BC SP 1 qqH 01 DE PUSH IX SP 2 IXL 11 Oil 101 2 4 15 10 HL SP 1 IXH 11 100 101 II AF PUSH IY SP 2 IYL II 111 101 2 4 15 SP I IYH II 100 101 POPqq qqH SP 1 II qq0 001 1 3 10 qqL SP...

Page 277: ... 110 000 2 4 16 If BC 0 HL HL I BC BC I Repeat until BC 0 t DD DE IIL 1 U 0 It IUI 101 2 4 16 DE DE I 10 101 000 HL HL 1 BC B I LDDR Dl HL U 0 0 II 101 101 2 5 21 IfBC0 DE DE I 10 III 000 2 4 16 IfBC O HL H1 1 BC BC I Repeat until BC 0 CPI A HL I I I I I II 101 101 2 4 16 HL HL 1 10 100 001 BC BC I 2 CD CPIR A HL I I I I I 11 101 101 2 5 21 If BC 0and A HL HL HL I 10 110 001 2 4 16 If BC Oor A HL ...

Page 278: ...dicatcd bits XOR s A A s 0 1 P 1 0 1 101 replace the 000 in CPs A s I I V I I I III the ADD set above INCr r r I I V I 0 I Off r 100 I 1 4 INC If L HL HL I I V 1 0 1 00 110 100 I 3 II INC IX d lX d I V 1 0 1 II Oil 101 3 6 23 IX d 1 011 I10 100 J INC UY d IY d I V t 0 I II Ill 101 3 6 23 IY d I 00 11 1 10 1 1 I C d 2 d I V I I I 1111 sl any utr HLI IX d IIY d as shown for INC Same format and state...

Page 279: ...ate acc two s 01 000 100 complement CCF CY r my t 0 X 00 i l l 111 1 1 4 Complement carry flag SCF CY 1 1 0 0 00 110 Ill 1 1 4 Set carry flag NOP No operation 00 000 000 1 1 4 HALT CPU halted 01 110 I10 1 1 4 DI IFF 0 11 110 011 1 1 4 El IFF 1 111 Oil 1 1 4 IM 0 Set interrupt 11 101 101 2 2 8 mode0 01 000 110 IM I Set interrupt 1 101 101 2 2 8 model 01 010 110 IM2 Set interrupt 1 101 101 2 2 8 mod...

Page 280: ...0 BC 01 DE 10 IX 11 SP ADD IY rr Y IY er I 0 X 11 111 101 2 4 15 Se Reg 00 eel 001 00 BC 01 DE 10 ly II SP INC ss ss ss 1 00 s0 011 1 1 6 INC IX IX IX 1 11 Oil 101 2 2 10 00 100 Oil INCIY IY Y 1 111 101 II 2 2 10 00 100 01l DEC as ss ss 1 00 sal Oil I 1 6 DEC IX IX IX 1 11011 101 2 2 10 00 101 Oil DECIY IY IY 1 II III 101 2 2 10 00 101 Oil Notes ss is any of the register pairs BC DE HI SP pp is an...

Page 281: ... 101 4 6 23 001 C O ixu nx a UY 11 001 O11 Ott E E d 100 H 00 000 110 1011 L RLC IY d t 1 P I 0 0 Il 111 101 4 6 23 111 A 11 001 Ott a 00 000 Ilo RL s 11 P 1 0 0 010 Instruction format and s s u ix m iv e states are as shown for RLC s To form new ORcode replace RRC s 1 I P I 0 0 001 000 of RLC s with shown code RR s 11 P 1 0 0 011 SLA s I 1 P I 0 0 100 SRA s ES 1 I P 1 0 0 101 SRL s I t P 1 0 0 11...

Page 282: ...X 0 1 11 111 101 4 5 20 000 0 11 001 Oil 001 1 010 2 y d Oll 3 01 b 110 100 4 101 5 110 6 111 7 SETb r rh I l 1 001 Oil 2 2 8 11 b r SET b HL HL b I I1 001 Ott 2 4 15 11 b 110 SET b IX d IX d b 1 II Ott 101 4 6 23 11 001 Ott d 11 b 110 SET b IY d IY d b 1 111 101 4 6 23 11 001 Ott d 11 b 110 RES b s 5b0 10 To form new OR s r HL code replace 11 IX d of SET b s with 1 flags and time IY d states for ...

Page 283: ...3 12 If condition is me PC PC e JR Z a If Z 0 00 101 000 2 2 7 It condition not met continue e 2 IfZ 1 2 3 2 Ifcondition is met PCPC e JR NZ a If Z 1 00 100 000 2 2 7 If condition not me continue a 2 If Z 0 2 3 12 If condition met PC PC e JP HL PC HL II 101 001 1 1 4 JP IX PC IX I I Ol 1 101 2 2 8 Il 101 001 JP IY PC IY II 111 101 2 2 8 11 101 001 DJNZ e B B I 00 010 000 2 2 8 1fB 0 If B 0 a 2 con...

Page 284: ... 1 5 If cc is false cc is false wntrwise otherwise 1 3 11 If cc is true same as cc Condition RET 000 NZ non zero 001 Z zero RETI Return from 101 101 2 4 14 010 011 NC non carry C carr interrupt 01 001 l01 y parity odd REIN Return from 11 101 101 2 4 14 01 PE parity even non maskable interrupt 01 000 101 110 111 P sign positive M sign negative RST p SP l PCH 11 t 111 1 3 11 SP 2 PCL PCH 0 PCL P P 0...

Page 285: ...01 2 5 20 C to A0 A7 B B 1 10 111 010 IfB 0 Bto A8 A15 HL HL 1 2 4 15 Repeat until If B 0 B 0 OUT n A n A I I 010 Oil 2 3 1 1 A All Arc to A8 _ A15 OUT C r C r 101 101 II 2 3 12 CtoA0 A7 01 r 001 Bto A8 A15 OUTI C HL I X X I X 11 101 101 2 4 15 C t All A7 B B I 10 100 Oil Bto A8 A15 HL HL I OTIR C HL I X X I X I1 101 101 2 5 20 C to A0 A7 B B 1 10 110011 lfBx0 Btu A8 A15 HL HL I 2 4 IS Repeat unti...

Page 286: ... BINARY AND HEXADECIMAL REPRESENTATION Binary Representation In binary positional notation is used similarly to decimal notation 1 2341o 4X 10 4 3X 101 30 2 X 102 200 I X 103 1000 1234 IL U I X 2 2 1 X 21 2 1 X 22 4 1 X 23 8 0X2 0 1 X 22 32 4710 295 ...

Page 287: ... 12 1100 C 13 1101 D 14 1110 E 15 1111 F Hexadecimal to Decimal Conversion A B 9 2 H t_ 16 POSITION 1 16 POSITION 16 16N 162 POSITION 256 POSITION 163 POSITION 4096 To convert 2X16 2X1 2 9X161 9X16 144 11 X 162 11 X 256 2816 10 X 16 10 X 4096 40960 43 922io Steps in Conversion 1 Multiply each digit weight by hex digit 2 Add to get total equal to equivalent decimal 296 ...

Page 288: ...C D E F 10 11 12 13 14 OPERAND 6 6 7 8 9 A B C D E F 10 11 12 13 14 15 1 7 7 8 9 A B C D E F 10 11 12 13 14 15 16 8 8 9 A B C D E F 10 11 12 13 14 15 16 17 9 9 A B C D E F 10 11 12 13 14 15 16 17 18 A A B C D E F 10 11 12 13 14 15 16 17 18 19 B B C D E F 10 11 12 13 14 15 16 17 18 19 1A C C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B D D E F 10 11 12 13 14 15 16 17 18 19 IA lB 1C E E F 10 11 12 13 1...

Page 289: ...APPENDIX E ASCII Character Code The ASCII character code is shown in Chart E 1 on the follow ing page 298 ...

Page 290: ...a A Z o u 0 n r E v 2 V J Q J h R 1 N N dp m Q U CD 2 X t X co W n w V 3 m U Q N p u 1 w vl Z u W N 0 V w c w 0 X W Cl 4 M V N U a X N 0 N CO K N 0 O u a Q 0 v O G O d a 0 O N l7 N O A 1101a X3H 1NV71UINDIS ISOW 299 ...

Page 291: ...ver Colorado 80206 MiniMicroMart Inc 1618 James Street Syracuse New York 13203 Quay Corporation P O Box 386 Freehold New Jersey 07728 Radio Shack A Division of Tandy Corporation One Tandy Center Fort Worth Texas 76102 S D Sales Company P O Box 28810K Dallas Texas 75228 Technical Design Labs Inc Research Park Bldg H 1101 State Road Princeton New Jersey 08540 Zilog Inc 10460 Bubb Road Cupertino Cali...

Page 292: ...mulator CPL 42 Conditional calls and returns 214 jumps 209 Condition codes 19 Controller 22 Counter timer circuit CTC 111 247 248 CPU 15 electrical specifications 30 31 registers 19 timing 30 31 CRC parity generation 252 Cromemco Inc 265 269 Cross assembler 137 Current assembler location 142 Cycle stealing 229 Daisy chained interrupt circuitry 37 Data bus 26 strings 192 197 structures 192 Debuggin...

Page 293: ...Initialized 152 Input and output data formats RAM ROM configuration 120 group 92 signals I R 28 Insert table entry actions 201 Instruction comparison 8008 8080 and Z 80 13 modification for VDT bit routine 188 set 55 92 Intel 8080 12 8008 11 4004 11 Interface signals and timing 26 40 Interfacing memory and I O devices to the Z 80 116 132 ROM and RAM 118 121 Interrupt 16 20 enable flip flop IFF 29 3...

Page 294: ...interrupts 106 108 NMOS 12 Nongenerative comment line 138 Nonmaskable always active interrupt 22 23 Acknowledge cycle NMI 32 cycle 38 39 No parity NP 209 Number bases representation of 141 Object module 137 144 Op code fetch cycle Ml 32 33 Operant 81 OS Z 80 operating system 257 Overflow conditions and P V flag 101 Pad a program 72 Page zero addressing modified 48 49 Paper tape reader controller 2...

Page 295: ...ing conditions 194 Subroutine GTADD action 187 operation jump call and return groups 208 218 use 211 216 Subtract flag N 19 SUPER BASIC 265 Symbolic assembly language 133 representation 139 141 Symbols 141 Table for binary search example 202 operations 197 204 search examples 117 routine 243 244 Technical Design Labs Inc TDL 260 265 Timing interface signals and 26 40 loop 234 Toggle 166 Toggled 17...

Page 296: ......

Page 297: ... operations list and table procedures subroutine use and 1 0 functions relative to instruction set groups Many examples of each operation are provided The I sst chapter in the section offers some commonly used subroutines written in Z 80 assembly language Section III discusses microcomputers built around the Z a0 Chapter 17 presents the Zilog products Including the microcomputer board products In ...

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