Z8
®
CPU
User Manual
UM001604-0108
Counters and Timers
80
Counters and Timers
Z8
®
CPU provides up to two 8-bit counter/timers, T0 and T1, each driven by its own 6-bit
prescaler, PRE0 and PRE1 (see
). Both counter/timers are independent of the
processor instruction sequence, that relieves software from time-critical operations such as
interval timing or event counting. Some MCUs offer clock scaling using the SMR. Refer
to the device product specification for clock available options.
Each counter/timer operates in either Single-Pass or Continuous mode. At the end-of-
count, counting either stops or the initial value is reloaded and counting continues. Under
software control, new values are loaded immediately or when the end-of-count is reached.
Software also controls the counting mode, how a counter/timer is started or stopped, and
its use of I/O lines. Both the counter and prescaler registers can be altered while the
counter/timer is running.
Counter/timers 0 and 1 are driven by a timer clock generated by dividing the internal clock
by four. The divide-by-four stage, the 6-bit prescaler, and the 8-bit counter/timer form a
synchronous 16-bit divide chain. Counter/timer 1 can also be driven by an external input
Figure 68. Counter/Timer Block Diagram
÷
2
OSC
D1 (SMR)
÷
16
D0 (SMR)
Clock
÷
4
Logic
Internal
Clock
External Clock
Internal Clock
Gated Clock
Triggered Clock
T
IN
P31
÷
4
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Write
Read
Write
Write
Read
Write
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
÷
2
Internal Data Bus
Internal Data Bus
T
OUT
IRQ
4
P36
IRQ
5
