Z8
®
CPU
User Manual
UM001604-0108
Input/Output Ports
47
Read/Write Operations
In the nibble I/O Mode, Port 0 is accessed as general-purpose register P0 (
00h
) with ERF
Bank set to 0. The port is written by specifying P0 as an instruction's destination register.
Writing to the port causes data to be stored in the port's output register.
The port is read by specifying P0 as the source register of an instruction. When an output
nibble is read, data on the external pins is returned. Under normal loading conditions this
is equivalent to reading the output register. However, for Port 0 outputs defined as open–
drain, the data returned is the value forced on the output by the external system. This may
not be the same as the data in the output register. Reading a nibble defined as input also
returns data on the external pins. However, input bits under handshake control return data
latched into the input register via the input strobe.
The Port 0–1 Mode resistor bits D1–D0 and D7–D6 are used to configure Port 0 nibbles.
The lower nibble (P00–P03) can be defined as inputs by setting bits D1 to 0 and D0 to 1,
or as outputs by setting both D1 and D0 to 0. Likewise, the upper nibble (P04–P07) can be
defined as inputs by setting bits D7 to 0 and D6 to 1, or as outputs by setting both D6 and
D7 to 0 (see
Handshake Operation
When used as an I/O port, Port 0 can be placed under handshake control by programming
the Port 3 Mode register bit D2 to 1. In this configuration, handshake control lines are
Figure 31. Port 0 Configuration with TTL Level Shifter
OEN
PIN
OUT
IN
TTL Level Shifter
