UM012811-0904
Z8 Compatibility
eZ8 CPU
User Manual
12
RELOCATION OF THE EZ8 CPU CONTROL REGISTERS
The four control registers within the eZ8 CPU have new addresses to take advantage of the
larger Register File.
Stack Pointer High and Low Byte Registers
The Stack Pointer Low Byte (SPL) now resides at address
FFFH
in the Register File. The
Stack Pointer High Byte (SPH) now resides at address
FFEH
.
Register Pointer
The Register Pointer (RP) now resides at address
FFDH
in the Register File.
Flags Register
The Flags Register (FLAGS) now resides at address
FFCH
in the Register File.
STACK POINTER COMPATIBILITY
The stack pointer is now 12-bits in length and given by {SPH[3:0], SPL[7:0]}. This
change allows the origin of the stack to be placed at any address from
000H
to
EFFH
where
general-purpose registers are available. Refer to the device-specific Product Specification
for available Register File addresses. All stack pointer operations occur within the Regis-
ter File address space.
RESET COMPATIBILITY
Unlike the Z8
®
CPU which uses a fixed reset address of
00CH
, the eZ8 CPU uses a vec-
tored reset. Program Memory stores the RESET vector at addresses
0002H
and
0003H
(most significant byte at
0002H
and least significant byte at
0003H
). When the eZ8 CPU
is reset it fetches the RESET vector at addresses
0002H
and
0003H.
The eZ8 CPU writes
the RESET factor to the Program Counter. The eZ8 CPU executes code at the new Pro-
gram Counter address.
INTERRUPT COMPATIBILITY
The interrupt table now resides at starting address
0008H
in Program Memory to accom-
modate the increased number of interrupts available with the eZ8 CPU.
