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③
The data sent from the PC is transferred sequentially from the small number of the port
for output. Port set for input is also sequentially taken from small number and sent to PC.
The data of each port is captured 4-bits at a time.
e.g)
When ports 1 and 2 are set for input, and ports 3 and 4 are set for output.
Order to send
to PC
Port data
Order to output
to the ZS-6222
Port data
1
Port_1 D7 to D4
1
Port_3 D7 to D4
2
Port_1 D3 to D0
2
Port_3 D3 to D0
3
Port_2 D7 to D4
3
Port_4 D7 to D4
4
Port_2 D3 to D0
4
Port_4 D3 to D0
0000 0001
D7
D0
0
1
0010 0011
D7
D0
2
3
1010 1011
D7
D0
A
B
1100 1101
D7
D0
C
D
1
2
3
4
ZS-6222
Input
Output
0123
ABCD
ＵＳＢ
5.2. Control signal
A control signal is displayed so that it can be synchronized with the connected device.
Signal Direction
Description
STB
OUT
ZS-6222 completes receiving all data from the PC and outputs a pulse signal
after parallel output.
External device can be used this signal for Latch-Clock.
TRG
OUT A pulse signal is output to an external device by “T” command.
CLR
OUT
A pulse signal is output to an external device by “C” command.
It is possible to be used resetting external devices.
LAH
IH
When the latch circuit is enabled setting by “L” command, latch input data
with this signal. Input a signal with a pulse width of 500µs or more.
Hote) The pulse width of the output can be set by command.
It is possible to be set 10µs, 100µs and 1ms.
