4-41
IM DLM3054-01EN
ID OR
This item is the same as that of the CAN bus trigger.
FDF
Set the FDF bit state as a trigger condition.
0 (CAN): When the FDF bit is dominant, the instrument assumes that the frame is a CAN bus signal frame and
triggers.
1 (CAN FD): When the FDF bit is recessive, the instrument assumes that the frame is a CAN FD bus signal
frame and triggers.
ESI(ErrorPassive)
The instrument triggers when the ESI bit is recessive (error passive).
Source (Source)
Select the trigger source. After selecting the trigger source, configure the trigger level, hysteresis, bit rate,
recessive level, HF rejection, and sample point.
Source (Source)
Set the trigger source to one of the settings below.
CH1 to CH4
Bit Rate (Bit Rate)
Select the CAN FD bus signal’s arbitration phase data transfer rate from one of the settings below.
250kbps, 500kbps, 1Mbps, User Define
If you select User Define, set the transfer rate in the range of 20 kbps to 1 Mbps in 0.1-kbps steps.
Sample Point (Sample Point)
You can set the reference that will be used to determine the bus level (recessive or dominant) of the CAN FD
bus signal’s arbitration phase in the range of 18.8 to 90.6% in 0.1% steps. The idea of sample point is the same
as CAN bus signals.
Data Bit Rate (Data Bit Rate)
Select the CAN FD bus signal’s data phase data transfer rate from one of the settings below.
500kbps, 1Mbps, 2Mbps, 4Mbps, 5Mbps, 8Mbps, User Define
If you select User Define, set the transfer rate in the range of 250 kbps to 10 Mbps in 0.1-kbps steps.
The data bit rate can be set as high as 16 times the arbitration phase bit rate.
Sample Point of the Data Phase (Sample Point)
You can set the reference that will be used to determine the bus level (recessive or dominant) of the CAN FD
bus signal’s data phase in the range of 18.8 to 90.6% in 0.1% steps. The idea of sample point is the same as
CAN bus signals.
If the data bit rate exceeds 16 times the bit rate, the rates are automatically adjusted according to the last set
value so that the relationship “data bit rate ≤ bit × 16” is maintained.
4 Triggering