6-3
IM 701310-17E
Status Reports
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App
Index
6.2 Status Byte
Status Byt
7
6 ESBMAV EES EAV 1
0
RQS
MSS
• Bits 0, 1, and 7
Not used (always 0)
• Bit 2 EAV (Error Available)
Set to 1 when the error queue is not empty. In other
words, this bit is set to 1 when an error occurs. See
the page 6-6.
• Bit 3 EES (Extend Event Summary Bit)
Set to 0 when the logical product of the extended
event register and the corresponding enable register
is 1. In other words, this bit is set to 1 when an
event takes place inside the instrument. See the
page 6-5.
• Bit 4 MAV (Message Available)
Set to “1” when the output queue is not empty. In
other words, this bit is set to 1 when there are data
to be transmitted. See the page 6-6.
• Bit 5 ESB (Event Summary Bit)
Set to 0 when the logical product of the standard
event register and the corresponding enable register
is 1. In other words, this bit is set to 1 when an
event takes place inside the instrument. See the
page 6-4.
• Bit 6 RQS(Request Service)/
MSS(Master Status Summary)
Set to 1 when the logical AND of the status byte
excluding Bit 6 and the service request enable
register is not 0. In other words, this bit is set to 1
when the instrument is requesting service from the
controller.
RQS is set to 1 when the MSS bit changes from 0 to
1, and cleared when serial polling is carried out or
when the MSS bit changes to 0.
Bit Masking
To mask a bit in the status byte so that it does not
cause an SRQ, set the corresponding bit of the service
request enable register to 0.
For example, to mask bit 2 (EAV) so that service is not
requested when an error occurs, set bit 2 of the service
request enable register to 0. This can be done using
the *SRE command. To query whether each bit of the
service request enable register is 1 or 0, use *SRE?.
For details on the *SRE command, see chapter 5.
Operation of the Status Byte
A service request is issued when bit 6 of the status
byte becomes 1. Bit 6 is set to 1 when any of the other
bits becomes a 1 (when the corresponding bit of the
service request enable register is also set to 1).
For example, if an event occurs and the logical AND
of the standard event register and the corresponding
enable register becomes a 1, then bit 5 (ESB) is
set to 1. In this case, if bit 5 of the service request
enable register is 1, bit 6 (MSS) will be set to 1, thus
requesting service from the controller.
In addition, you can also check what type of event
occurred by reading the contents of the status byte.
Reading from the Status Byte
The following two methods are provided for reading the
status byte.
• Inquiry using the *STB? query
Making an inquiry using the *STB? query sets bit
6 to MSS. This causes the MSS to be read. After
completion of the read-out, none of the bits in the
status byte will be cleared.
• Serial polling
Execution of a serial polling changes bit 6 to RQS.
This causes RQS to be read. After completion of
the read-out, only RQS is cleared. It is not possible
to read MSS using serial polling.
Clearing the Status Byte
No method is provided for forcibly clearing all the bits
in the status byte. The bits that are cleared for each
operation are shown below.
• When a query is made using the *STB?
command
No bits are cleared.
• When serial polling is executed
Only the RQS bit is cleared.
• When a *CLS command is received.
When the *CLS command is received, the status
byte itself is not cleared, but the contents of the
standard event register (which affects the bits
in the status byte) are cleared. As a result, the
corresponding bits in the status byte are cleared,
except bit 4 (MAV), since the output queue cannot
be emptied by the *CLS command. However,
the output queue will also be cleared if the *CLS
command is received just after a program message
terminator.
