Yamaha YSP-1, Service Manual

Page: 51 / 68

A
1
2
3
4
5
6
7
8
9
10
B C D E F G H I J K L M N
YSP-1
SCHEMATIC DIAGRAM (DSP 1/2)
51
★ All voltages are measured with a 10M Ω /V DC electronic volt meter.
★
Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
Page 54
to AMP_CB3 to AMP_CB3
F2
Page 54
to DSP_CB302 (T, A, G, J models) G1
Page 54 F2
This part can not be supplied
この部品はパーツ供給しません
IC3 and IC4 can not be supplied. / IC3及びIC4はパーツ供給しません。
This part can not be supplied
この部品はパーツ供給しません
This part can not be supplied
この部品はパーツ供給しません
This part can not be supplied
この部品はパーツ供給しません
This part can not be supplied
この部品はパーツ供給しません
This part can not be supplied
この部品はパーツ供給しません
This part can not be supplied
この部品はパーツ供給しません
This part can not be supplied
この部品はパーツ供給しません
This part can not be supplied
この部品はパーツ供給しません
POINT A-2 pin 3 of IC5
3.3
3.0
3.2
3.1
3.1
0
3.1
3.1
3.2
3.1
3.1
0
3.1
3.3
3.1
3.1
0
3.2
3.2
0
3.2
0
0
0
0
3.2
3.2
3.3
3.1
0
3.1
3.1
3.2
3.1
3.1
0
3.1
3.1
3.2
3.2
3.3
0 0
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.0
3.2
3.2
0
3.2
0
3.2
0
0
0
0
0
0
0
0
0
3.2
3.2
0
3.2
0
0
1.6
1.6
2.1
3.1
3.2
3.2
0
0
3.1
0
3.3
3.2
0
3.2
3.3
0
3.3
A-2
3.3
3.3 1.7
0
1.7 1.6
1.6
3.3
3.3 1.7 1.7
3.3
1.6
1.6
3.2
3.2
0
3.2
3.2
1.6
0
0
0
1.3
2.6
2.6
0
1.3
0
3.3
3.3
3.3
1.3
2.5 2.5
2.5
3.3
2.5
2.6
3.2
3.3
0
0
0
0
0.9 3.3
2.8
3.3
3.3
3.3
0
0
0
0
0
2.6
2.6
2.6
2.6
0
1.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
2.8
3.3
3.3
3.3
0
0
0
1.3
3.3
0
1.3
1.3
1.3
1.3
1.3
0
3.0 0 3.0
3.3 3.3
0
3.3 0.1 3.3
0
3.0
3.2
1.6 1.6 1.6
3.1
3.1
3.2
3.1
0
3.1
3.1
3.2
3.1
0
3.2
3.2
0
0
0
0
0
0
0
3.2
0
3.1
3.2
3.2
3.0
0
3.0
3.0
3.2
3.2
3.1
0
3.1
0
L
SYNCHRONOUS
DRAM
PWM
IC1 : MT48LC2M32B2P-6
SYNCHRONOUS DRAM
IC2 : MBM29LV160BE-70
16M-bit, 3.0 V-only Flash memory
11
RAS#
CAS#
CLK
CS#
WE#
CKE
8
A0-A10,
BA0, BA1
DQM0-
DQM3
13
256
(x32)
8192
I/O GATING
DQM MASK LOGIC
READ DATA L ATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(2,048 x 256 x 32)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
2048
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0-
DQ31
32
32
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
32
BANK1
BANK0
BANK2
BANK3
11
8
2
4 4
2
REFRESH
COUNTER
11
11
MODE REGISTER
CONTROL
LOGIC
COMMAND
DECODE
ROW-
ADDRESS
M UX
ADDRESS
REGISTER
COLUMN-
ADDRESS
COUNTER/
LATCH
V DD
DQ0
V DD Q
DQ1
DQ2
V SS Q
DQ3
DQ4
V DD Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V DD
NC
DQ16
V
SS Q
DQ17
DQ18
V
DD Q
DQ19
DQ20
V
SS Q
DQ21
DQ22
V
DD Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43 86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44 V SS
DQ15
V
SS Q
DQ14
DQ13
V
DD Q
DQ12
DQ11
V
SS Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD Q
DQ30
DQ29
V
SS Q
DQ28
DQ27
V
DD Q
DQ26
DQ25
V
SS Q
DQ24
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25 A 15
A 14
A 13
A 12
A 11
A 10
A 9
A 8
A 19
N.C.
WE
RESET
N.C.
N.C.
RY/BY
A 18
A 17
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A16
BYTE
VSS
DQ 15/A-1
DQ 7
DQ 14
DQ 6
DQ 13
DQ 5
DQ 12
DQ 4
VCC
DQ 11
DQ 3
DQ 10
DQ 2
DQ 9
DQ 1
DQ 8
DQ 0
OE
VSS
CE
A 0
A-1
VSS
VCC
WE
CE
A0 to A19
OE
State
Control
Command
Register
Erase Voltage
Generator
Input/Output
Buffer
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
DQ 0 to DQ 15
Low VCC Detector
Program Voltage
Generator
Timer for
Program/Erase
Chip Enable
Output Enable
Logic
Data Latch
BYTE
RESET
RY/BY
Buffer
RY/BY
STB
STB
Address
Latch
I/O
Block
ORP ORP
16
16
GOE0 GOE1 V
CC
GND TCK TMS TDI TDO
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
ORP ORP
16
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
I/O Bank 0 I/O Bank 1
I/O
Block
36
36
CLK0/I CLK1/I CLK2/I CLK3/I
16
16
Global Routing P
ool
VCCO0 GND V
CCO1
GND
16 16
16
IC6 : LC4032V-75TN48C
Complex Programmable Logic Device
T_SUNT
Bias UVLO
BG GOOD
Delay
VIN UVLO
Comparator
VIN
Falling
Edge
Delay
s 1–4
SS_DIS
VIN_UVLO
0.8 V
Enable
Comparator
VIN
+
–
MUX
Error
Amplifier
Reference/DAC
SHUTDOWN
PWM
Comparator
Rising
Edge
Delay
Rising
Edge
Delay
R Q
S
OSC
Ct
Iset
SS/ENA
SHUTDOWN
ILIM
Comparator
Deadtime
SHUTDOWN
Highin
VI(LIM)
Sampling
Highin Highdr
SHUTDOWN
VPHASE
SHUTDOWN
Falling
Edge
Delay
SHUTDOWN
VSENSE
Vpgd
Powergood
Comparator
s 20–50
REG UVLO UVLO
VBIAS
VBIAS
VIN
BOOT
PH
PWRGD
RT SYNC
AGND
VSENSE
L(out)
Co
VO
Logic
VIN
PGND
Offset
Highdr
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
IC7, 8 : TPS54310PWPR
Low-input-voltage high-output-current synchronous-buck PWM converter
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
†Current Sense
IC9 : TPS2034D
POWER-DISTRIBUTION SWITCHES
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
IC5 : SN74LVC74APWR
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS