Yamaha TSS-10, Service Manual

Page: 25 / 40

A B C D E F G H I J K L
TSS-10
25
SCHEMATIC DIAGRAM (DSP)
1
2
3
4
5
6
7
8
9
DSP/DOLBY/DTS
★
Unless otherwise specified, all resistors are 1608 size chip resistors.
★
Unless otherwise specified, all capacitors are 1608 size chip capacitors.
★
Flame proof carbon resistors are all 1/4W.
● 指示のない抵抗はすべて1608サイズチップ抵抗です。
● 指示のないコンデンサはすべて1608サイズチップコンデンサです。
● 不燃化カーボン抵抗はすべて1/4Wです。
★
All voltage are measured with a 10M
Ω
/V DC electric volt meter.
★
Components having special characteristics are marked
s
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
Point 1 Pin 1 of IC1
Point 3 collector of Q1 and emitter of Q2
Point 2 Pin 13 of IC2
POWER ON
(Connect the power cord)
3.00S
POWER OFF
(Disconnect the power cord)
At start-up
A Q1 C
B Q2 E
A Q1 C
B Q2 E
IC4: TA48M033F
Voltage Regulator
1
Short
Protection
Excessive Voltage Protection
Over Heat Protection
INPUT
2 OUTPUT
3 GND
+
–
IC3 : CS4228A
ADC/DAC
∆∑
DAC #1 DIGITAL VOLUME
SERIAL A
UDIO D
A
T
A INTERF
A
CE
DIGIT
AL FIL
TERS
WITH DE-EMPHASIS
DIGIT
AL FIL
TERS
ANALOG LO
W P
ASS AND OUTPUT ST
A
GE
CONTROL PORT
6
3
1
4
10 7 22
11 12 13
23
FL
18 FILT
∆∑
DAC #2 DIGITAL VOLUME
24 FR
∆∑
DAC #3 DIGITAL VOLUME
25 SL
∆∑
DAC #4 DIGITAL VOLUME
26 SR
∆∑
DAC #5 DIGITAL VOLUME 27
CENTER
∆∑
DAC #6 DIGITAL VOLUME 28
SUB
LEFT ADC
19
AINL-
20
AINL+
LEFT ADC
17
AINR-
16 AINR+
MCLK
DGND
A
GND
LRCK
SDIN1
SDIN3
SDOUT
5
2
SCLK
SDIN2
SCL/CCLK SD
A/CDIN
AD0/CS
MUTE CONTROL
CLOCK MANAGER
15
MUTEC
14
RST
8
VD
9
VL
21
VA
IC5: PQ025EZ5MZP
Voltage Regulator
1 Vin 3 Vo
2
Vc
5
GND
IC6: TC74HCT08AF
Quad 2-Input And Gate
Vcc 14
4B 13
4A 12
4Y 11
3B 10
3A 9
3Y 8
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
IC7: S-29390AFJA
CMOS 4kbit Serial EEPROM
5
2
7
6
8
1
3
4
DI
Vcc
GND
DO
TEST
NC
CS
SK
Memory array Address decoder
Data register Output buffer
Mode decode logic
Clock generator
IC8~12: NJM4558M
Dual OP-Amp
– +
OUT
1
–IN
1
–V
CC
+V
CC
OUT
2
1
2
3
4 5
+IN
1
–IN
2
+IN
2
– +
6
7
8
16bit
µ
-COM
EEPROM
RESET
POWER DOWN
DETECT
REGULATOR
ADC/DAC
P
age 26
to AMP (CB301)
B2
Page 26
to AMP (CB302)
B5
Page 26
to AMP (CB304)
C6
P
age 27
to AMP (CB307)
G3
3
FRONT L
CENTER
CENTER
ANALOG INPUT L
SURROUND L
FRONT L
SURROUND L
2
1
A
B
4.4
12.0
0
4.4
4.4
4.4
12.0
0
4.4
4.4
4.4
12.0
0
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
0
12.0
4.4
4.4
4.4
4.4
4.4
5.1 5.1
5.1
2.3
2.3
2.3 2.3
5.1
4.4
4.4
4.4
4.4
0
12.0
4.4
1.2
~
1.1
1.3
1.7
1.7
0
5.1
3.3
1.6
4.9
0
4.9
4.9
2.4
2.4
2.4
2.4
2.4
2.4
0
5.1
2.3
2.3
2.7
2.3
2.3
0
3.3
3.3
0
0
5.1
3.3 5.1
2.5
2.5 4.9 5.1
15.0 15.0
14.3
0 0
2.5
7.0
7.0 7.0
0
0
0
0
0
4.8
5.1
0
5.0 0
0
4.9
5.0
0
0
4.0
0
5.0
0
0
5.0
0
0
0
0
0
0
0
0
0
5.0
0
0
0
0
0
0
0
0
0
3.3
0
3.2
0
2.3
4.5
4.9
0
2.5
3.3 1.6 1.5
0 0 0 0 0 0 0
3.3
0 0 0 0
1.0 3.3 1.9 1.8
0
4.9 3.3 3.3 0.2 1.3
0
0
4.0
0
2.5
0
0
2.5
1.7
1.7
1.6
0
1.2
~
1.1
3.3
0
2.5
3.3
0
3.3
0
3.3
5.0
2.2
1.6
3.3
0
3.3
5.0
2.3
1.6
3.3
0
0
4.9
0
4.9
0
4.9
0
0
0
0
4.9
2.4
0
2.4
0 0 0
4.9 2.4 2.4
0
1.6 1.6
0
5.2 4.9 4.9 4.9
1.6 1.5 4.9 2.3 4.5
0 0
3.3 4.8
0
2.3
0
2.1
0 0 0
4.9 4.9 3.2
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
0
4.9
4.9
DTA123JKA
DTA123JKA
0.033
0.33
w w w . x i a o y u 1 6 3 . c o m
Q Q
3 7 6 3 1 5 1 5 0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL 13942296513 QQ 376315150 892498299 TEL 13942296513 QQ 376315150 892498299
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