Yamaha RX-V681, Service Manual

Page: 114 / 170

A
1
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10
N M L K J I H G F E D C B
114
RX-V681/RX-A760
M T _ N _ Z 2
M T _ S W
M T _ Z 2
M T _ S B
M T _ 5 C H
EX_MOS
I
EX_SCK
D [ 8 ]
D [ 4 ]
D [ 7 ]
] 4 1 [ D ] 9 [ D
D [ 1 1 ]
D [ 2 ]
D [ 6 ]
D [ 1 2 ]
D [ 3 ]
D [ 1 5 ]
D [ 0 ]
D [ 1 ]
] 3 1 [ D ] 0 1 [ D
D [ 5 ]
M C B U S _ N _ R D
F P G A _ N _ W R
F P G A _ N _ C S
L M T _ D C
L M T _ O L V
AD1_CO
M
TUN_SC
L
TUN_SD
A
TUN_N_RS
T
W A K E U P _ I N T
M T _ N _ S W
M T _ N _ 5 C H
M T _ N _ S B
L M T _ P S 1
L M T _ P S 2
AMP_OL
V
DC_PRT
L M T _ O L V
L M T _ D C
TUN_N_IN
T
FLD_N_RS
T
FLD_N_C
S
FLD_SC
K
FLD_MOS
I
MIC_N_DE
T
REM_IN
1
ISEL_R
A
ISEL_R
B
KY_AD1 KY_AD2 VOL_RA VOL_RB PD_LED
FLD_PO
N
STBY_LE
D
E X _ S C K
E X _ M O S I
F L D _ S C K
F L D _ M O S I
FLD_PO
N
D I R _ N _ R S T
AD_SEL_C AD_SEL_B AD_SEL_A AD_SEL_A AD_SEL_B AD_SEL_C
LMT_I
AD2_CO
M
VDEC_N_RST FPGA_MOS
I
FPGA_SCK FPGA_N_CFG
PS2_PR
T
PA_B_R
Y
AMP_LM
T
MODEL
TES
T
DSP_PON MT_DA DSP1_N_RS
T
DSP1_N_CS DSP_SCK DSP_MOS
I
DSP_MIS
O
DSP1_N_SPIRDY
2 3 2 C _ D B G _ M I S O
DFF_FROM_N_RST
THM
1
DC_PRT
PS1_PR
T
AMP_OL
V
MT_5CH
MT_SB MT_Z2 MT_SW I_PRT
PS2_PR
T
HP_N_DE
T
PS2_PR
T L
C
S
_
V
DL
C
S
_
V
D
A
D
S
_
V
DA
D
S
_
V
D
RM+ RM-
DV_SDA DV_SCL
HWDET
L M T _ P S 3
SPRY_5CH
AMP_LM
T
HDMI_SCL HDMI_SDA HTX_N_IN
T
HAU_N_IN
T
HSW1_N_INT HRX_N_IN
T
HSWI2C_O
N
FLP_PO
N
FHDMI_N_IN
T
HSW_N_RS
T
HDIN_HPD
1
HSW_PON
HDIN_HPD
2
HDIN_HPD
3
HRTX_N_RST HDMI_PON
HWDE
T
A [ 5 ]
D [ 1 3 ]
A [ 4 ]
A [ 3 ]
A [ 2 ]
A [ 1 ]
D [ 0 ]
D [ 8 ]
A [ 1 2 ]
A [ 2 2 ]
A [ 1 4 ]
A [ 2 0 ]
A [ 2 1 ]
A [ 9 ]
A [ 1 0 ]
A [ 1 3 ]
A [ 1 1 ]
A [ 1 9 ]
A [ 1 8 ]
D [ 6 ]
D [ 1 4 ]
D [ 1 ]
D [ 7 ]
D [ 9 ]
D [ 1 5 ]
D [ 2 ]
D [ 1 0 ]
A [ 1 7 ]
D [ 1 1 ]
A [ 1 6 ]
D [ 3 ]
A [ 1 5 ]
D [ 1 2 ]
A [ 8 ]
A [ 6 ]
D [ 4 ]
A [ 7 ]
D [ 5 ]
DV_PO
N
VID_PON HDMI_PO
N
DV_PON DV_PON DV_PON
VID_PO
N
232C_MIS
O
232C_MOS
I
EEP_N_CS EEP_MISO
D[0
]
D[1
]
D[2
]
D[3
]
D[4
]
D[5
]
D[6
]
D[7
]
D[8
]
D[9
]
D[10
]
D[11
]
D[12
]
D[13
]
D[14
]
D[15
]
NCPU_SPI_MOS
I
NCPU_SPI_MIS
O
NCPU_SPI_SC
K
FLASH_N_C
S
MCBUS_N_R
D
FLASH_N_W
R
D [ 5 ]
D [ 1 3 ] D [ 1 0 ]
D [ 1 ]
D [ 0 ]
D [ 1 5 ]
D [ 3 ]
D [ 1 2 ]
D [ 6 ]
D [ 2 ]
D [ 1 1 ]
D [ 1 4 ] D [ 9 ]
D [ 7 ]
D [ 4 ]
D [ 8 ]
DFF_N_CS NCPU_AMUTE SWV SWDIO SWCLK
NCPU_ADT_MUT
E
NCPU_VBUSDR
V
I_PR
T
LMT_
I
HP_N_DET
S W C L K
S W D I O
S W V
M I C _ N _ D E T
E X _ M O S I
E E P _ M I S O
E X _ S C K
2 3 2 C _ D B G _ M O S I
2 3 2 C _ D B G _ M I S O 2 3 2 C _ D B G _ M I S O
2 3 2 C _ M O S I
2 3 2 C _ M I S O
2 3 2 C _ D B G _ M I S O
T U N _ N _ I N T
N C P U _ M O S I
N C P U _ M I S O
VOL_SC
K
VOL_MOSI
V O L _ S C K
V O L _ M O S I
W A K E U P _ I N T
+ 3 . 3 S _ P O N
D I R 1 _ N _ I N T
M T _ N _ S B _ P O
M T _ S B _ P O
P S 3 _ P R T
D S P 1 _ N _ I N T
D S P 2 _ N _ R S T
D S P 1 _ N _ R S T
1
D
A
_
Y
K1
D
A
_
Y
K
2
D
A
_
Y
K2
D
A
_
Y
K
AD1_CO
M
AD2_CO
M
VOL_RB VOL_RA
ISEL_R
B
ISEL_R
A
DIR1_N_C
S
DSP2_N_SPIRD
Y
DSP1_N_C
S
MT_D
A
HAU_N_IN
T
HRX_N_IN
T
HTX_N_IN
T
TUN_SC
L
TUN_SD
A
DACZ2_N_M
T
A
[1]
A
[2]
A
[3]
A
[4]
A
[5]
A
[6]
A
[7]
D F F _ N _ C S
A [ 2 ]
A [ 1 ]
D F F 1 _ C L K
D F F 2 _ C L K
D F F 1 _ C L K
DFF1_CLK DFF2_CLK DFF_FROM_N_RS
T
FPGA_MOSI
FPGA_SC
K
DV_SD
A
DV_SC
L
HDMI_SD
A
HDMI_SC
L
A [ 8 ]
A [ 9 ]
A [ 1 0 ]
A [ 1 1 ]
A [ 1 2 ]
A [ 1 3 ]
A [ 1 4 ]
A [ 1 5 ]
A [ 1 6 ]
A [ 1 7 ]
A [ 1 8 ]
A [ 1 9 ]
A [ 2 0 ]
A [ 2 1 ]
A [ 2 2 ]
F P G A _ N _ C S
N C P U _ N _ I N T
F L A S H _ N _ C S
H S W I 2 C _ O N
F H D M I _ N _ I N T
M C B U S _ N _ W R
F P G A _ N _ W R
F L A S H _ N _ W R
M C B U S _ N _ R D
NCPU_N_RST USB_VBUS_PON
D F F _ N _ W R
BOO
T
DSP_MOS
I
DSP_MIS
O
DSP_SC
K
N C P U _ S P I _ N _ C S
NCPU_PON
A D _ S E L _ A
A D _ S E L _ B
A D _ S E L _ C
E E P _ N _ C S
H S W 1 _ N _ I N T
N P D A _ S E L
A D T _ S E L
N P S E L _ N _ O E
F L D _ P O N
F L D _ N _ R S T
F L P _ P O N
F L D _ N _ C S
D S P _ P O N
D F F _ F R O M _ N _ R S T
A D T _ N _ E N
+ 3 . 3 D _ P O N
T U N _ N _ R S T
P R Y
P A _ B _ R Y
P D _ L E D
H R T X _ N _ R S T
H D I N _ H P D 1
H D I N _ H P D 2
H D I N _ H P D 3 H D M I _ P O N
H S W _ N _ R S T
H S W _ P O N
D C _ T R G 1
F P G A _ N _ C F G
V I D _ P O N V D E C _ N _ R S T
D A C _ P O N
D A C Z 2 _ P O N
+ 3 . 3 M S _ P O N
TES
T
THM
1
THM
4
THM
3
PS2_PR
T
PS1_PR
T
AUD_DE
T
USB_VBUS_PRT
PS3_PR
T
L M T _ P S 3
L M T _ P S 1
L M T _ P S 2
DACZ2_PO
N
DAC_PON +3.3D_PO
N
USB_VBUS_PON PR
Y
ACPWR_DE
T
DC_TRG1 RM
+
RM
-
DIR_N_RS
T
DIR1_N_C
S
DSP_SCK DSP_MOSI DSP_MISO DACZ2_N_M
T
ADT_SEL ADT_N_EN NPDA_SEL NPSEL_N_O
E
DSP2_N_RS
T
DSP2_N_C
S
DSP2_N_SPIRD
Y
DSP1_N_IN
T
DIR1_N_IN
T
NCPU_N_IN
T
NCPU_ADT_MUT
E
NCPU_PHOL
D
NCPU_SPI_SCK NCPU_SPI_MOS
I
NCPU_SPI_MIS
O
NCPU_SPI_N_C
S
NCPU_N_RS
T
NCPU_AMUT
E
NCPU_MOS
I
NCPU_MIS
O
NCPU_VBUSDRV NCPU_PON DSP_PON
SPRY_Z2&FP SPRY_SB&BA
M C P U _ N _ R S T
M C P U _ N _ R S T M C P U _ N _ R S T
MCPU_N_RS
T
TEST USB_VBUS_PRT
MT_N_H
P
AUD_DE
T
MT_SB_P
O
THM4
M T _ N _ S B _ P O
STBY_LED
S P R Y _ 5 C H
M T _ N _ S B
M T _ N _ 5 C H
S P R Y _ Z 2 & F P
DSP1_N_SPIRD
Y
DSP2_N_C
S
M T _ N _ H P
S P R Y _ S B & B A
M T _ N _ S W
M T _ N _ Z 2
AMP_LM
T
NCPU_PHOLD
A C P W R _ D E T
R E M _ I N 1
THM
3
B O O T
2 3 2 C _ D B G _ M O S I
HDMI_PON
DSP_NI
C
DSP_NIC
+ 3 . 3 S _ P O N
MODE
L
C792
1/25
100K
R853
C79
0
0.1/10(BJ)
100P(CH)
C82
9
D G N D
R 7 5 2
1 K
C 7 5 6
1 0 0 0 P ( B )
R 7 5 0
1 K
R76
8
no_use
R 8 0 4
2 2 0 K X 4
4 . 7 K
R 8 5 8
1000P(B
)
C84
7
+3.3
S
8 5 7 Q
R L T B U 6 7 5 1 A
D G N D
1000P(B
)
C83
6
IC9
2
V +
5
1K
R77
3
C 7 5 8
1 0 0 0 P ( B )
+ 3 . 3 M
R 7 8 2
1 0 0 X 4
I C 9 1
T C 7 S H 8 6 F U
2
1
4
R
877
18
K
C
797
1/25
4 5 7 Q
R L T B U 6 7 5 1 A
R76
0
no_use
4 . 7 K
R 8 5 7
D
7
5
0
R
B
5
2
1
S
-
3
0
T
E
6
1
Q 7 5 3
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2 C 2
C 1
1 0 K
R 7 8 3
C 8 1 5
n o _ u s e
+ 3 . 3 S
+3.3
S
D G N D
DSP1_N_CS
D G N D
6 5 7 Q
R L T B U 6 7 5 1 A
IC9
1
V -
3
R
759
10
K
D G N D
4 7 K
R 8 2 6
R 7 7 7
1 0 0 X 4
+ 3 . 3 S
1000P(B
)
C84
6
L75
0
BKP1005HS680-T
+3.3
S
C 7 6 7
1 0 0 0 P ( B )
+ 3 . 3 S
DGN
D
1000P(B
)
C83
4
DGND
1
0
K
R
7
6
3
C 8 2 1
n o _ u s e
R
7
6
5
1
0
K
1000P(B)
C83
1
C 8 2 8
n o _ u s e
D G N D
A [ 0 - 2 3 ]
IC9
2
V -
3
FPGA_N_CFG
D [ 0 - 1 5 ]
R 7 5 1
9 . 1 K
100
R77
2
1000P(B
)
C84
3
1000P(B
)
C83
7
D
GND
4 . 7 K
R 8 5 6
C76
3
0.1/10(BJ)
C794
1
/25
DGN
D
R 8 0 8
2 2 0 K X 4
DSP_SCK DSP1_N_INT
M C B U S _ N _ R D
R82
7
10
D G N D
DV_SCL DSP_MOSI
F P G A _ N _ C S
DGN
D
+ 5 . 6 V
+ 3 . 3 S
R87
1
33
1000P(B)
C80
9
+ 5 . 6 V
R 8 4 6
2 . 2 K
100K
R852
C793
1/25
C
7
9
8
4
.
7
/
6
.
3
D G N D
C 7 6 6
1 0 0 0 P ( B )
R878 10
K
+ 3 . 3 M
C 8 1 0
n o _ u s e
FPGA_MOSI
+ 3 . 3 S
IC93
4
C 8 1 8
n o _ u s e
C 8 1 6
n o _ u s e
+3.3
S
R 8 9 0
3 3
9 5 7 Q
R L T B U 6 7 5 1 A
D G N D
IC79
TC74VHC273FT
1
C L R
2
Q 1
3
D 1
4
D 2
5
Q 2
6
Q 3
7
D 3
8
D 4
9
Q 4
1
0
G N D
1
1 C K
1
2 Q 5
1
3 D 5
1
4 D 6
1
5 Q 6
16
Q 7
17
D 7
18
D 8
19
Q 8
20
V C C
DSP1_N_RST
1
00K
R
855
C 7 6 0
1 0 0 0 P ( B )
C 8 2 5
n o _ u s e
C 7 7 2
0 . 1 / 1 0 ( B J )
1
00K
R
854
C 8 2 2
n o _ u s e
IC9
1
V +
5
TP754
D G N D
C 7 5 9
1 0 0 0 P ( B )
C 7 6 2
1 0 0 0 P ( B )
VDEC_N_RST
D G N D
+ 3 . 3 S
C803
4.7/6.
3
FPGA_SC
K
1000P(B
)
C84
0
C 7 5 5
1 0 0 0 P ( B )
1K
R77
0
R 8 6 1
4 7 0
C807
1000P(B)
+ 3 . 3 S
+5.6
V
Q 7 5 1
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2 C 2
C 1
+ 3 . 3 M
R88
8
100X
4
C 7 5 2
1 0 0 0 P ( B )
C 8 2 3
n o _ u s e
C76
9
33/1
0
C
795
1
/25
100
K
R78
4
+3.3
S
R 8 6 3
4 7 0
C 7 6 5
1 0 0 0 P ( B )
+ 3 . 3 S
+ 3 . 3 M
1000P(B)
C80
8
+ 3 . 3 S
+3.3
M
+ 5 . 6 V
7 5 7 Q
R L T B U 6 7 5 1 A
DGN
D
10
0
R790
1000P(B
)
C84
4
R 8 8 9
3 3
C 8 2 6
n o _ u s e
D G N D
+ 3 . 3 M
Q 7 5 0
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2 C 2
C 1
C 8 1 2
n o _ u s e
C 8 0 1
0 . 1 / 1 0 ( B J )
I C 9 3
T C 7 W H 1 2 6 F U ( T E 1 2
5 3
7
C 8 2 4
n o _ u s e
C 8 1 1
n o _ u s e
+ 3 . 3 M
C796
0.1/10(BJ
)
100P(CH)
C83
0
1000P(B
)
C83
8
1000P(B
)
C84
2
R 8 6 2
4 7 0
DSP1_N_SPIRD
Y
C 8 2 7
n o _ u s e
I C 7 6 S N 7 4 L V 4 0 5 1 A P W R
1
Y4
2
Y6
3
COM
4
Y7
5
Y5
6 7 8
1 1 0 1 9 1 2
Y3
1 3
Y0
1 4
Y1
1 5
Y2
1 6
VCC
D G N D
R866
220K
F P G A _ N _ W R
+ 3 . 3 M
DGN
D
10K R875
DSP_PO
N
+ 3 . 3 M
R88
1
100X
4
D G N D
R75
4
no_use
C 7 5 3
1 0 0 0 P ( B )
IC93
8
D G N D
TP75
8
C79
1
0.1/10(BJ)
DGND
C806
no_use
D G N D
C 8 1 3
n o _ u s e
1000P(B
)
C84
8
R 8 4 9
3 3
Q 7 5 5
A 1 5 7 6 U B T L R
R
753
10
K
C 8 1 9
n o _ u s e
C 7 7 5
0 . 1 / 1 0 ( B J )
R 8 4 5
2 . 2 K
1000P(B)
C83
9
C 7 5 1
1 0 0 0 P ( B )
D G N D
+ 3 . 3 S
R86
7
100X
4
DGND
0
J84
0
DV_SD
A
C 8 0 2
0 . 1 / 1 0 ( B J )
+ 5 . 6 V
MT_DA
C 7 5 7
1 0 0 0 P ( B )
D G N D
C75
4
0.1/10(BJ)
R 8 9 6
n o _ u s e
R 8 4 8
4 7 0 K
Q 7 6 0
C4081UBTL
R
1
0
K
R
7
6
7
3
3
K
R
7
7
6
+ 3 . 3 M
C 7 7 1
0 . 1 / 1 0 ( B J )
C 7 6 4
1 0 0 0 P ( B )
DGN
D
C799 1/25
1000P(B
)
C84
5
1K
R77
1
1000P(B
)
C84
1
4.7
K
R77
4
I C 9 2
S N 7 4 L V C 1 G 1 7 D C K R
2 4
I C 7 8 S N 7 4 L V 4 0 5 1 A P W R
1
Y4
2
Y6
3
COM
4
Y7
5
Y5
6 7 8
1 1 0 1 9 1 2
Y3
1 3
Y0
1 4
Y1
1 5
Y2
1 6
VCC
C 8 1 4
n o _ u s e
D G N D
DSP_MIS
O
I C 9 3
T C 7 W H 1 2 6 F U ( T E 1 2
2 6
1
1000P(B
)
C83
5
1K
R76
9
1000P(B)
C83
2
D G N D
TP752
C 8 2 0
n o _ u s e
IC81
TC74VHC273FT
1
C L R
2
Q 1
3
D 1
4
D 2
5
Q 2
6
Q 3
7
D 3
8
D 4
9
Q 4
1
0
G N D
1
1 C K
1
2 Q 5
1
3 D 5
1
4 D 6
1
5 Q 6
16
Q 7
17
D 7
18
D 8
19
Q 8
20
V C C
4 . 7 K
R 8 5 9
+ 3 . 3 D S P
C 8 1 7
n o _ u s e
D G N D
R 7 7 9
1 0 0 X 4
DGN
D
R 7 8 1
1 0 0 X 4
D G N D
+ 3 . 3 M
Q 7 5 2
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2 C 2
C 1
R86
8
100X
4
R 8 2 5
1 M
C B 7 8
P H I
V B 3 9 0 8 0
1 2 3 4 5 6 7 8 9
10 11 12
R 9 0 3
4 7 0 K
3 3 0
R 9 0 2
Q 7 6 3
A 1 5 7 6 U B T L R
+3.3
S
ADCVBS AD
Y
ADP
b
ADP
r
+ 3 . 3 V
D G N D
P L 3 . 0
P L 0 . 3
C 8 4 9
n o _ u s e
C 8 5 0
n o _ u s e
C 8 5 1
n o _ u s e
Q 7 6 4
n o _ u s e
+ 3 . 3 S
0
J75
5
5 6 7 Q
R L T B U 6 7 5 1 A
D G N D
L75
2
BLM21PG600SN1D
HDMI_SD
A
HRTX_N_RST HAU_N_INT HDIN_HPD2 HDIN_HPD1 HDIN_HPD3 HRX_N_INT HTX_N_INT HSW1_N_INT HSW_N_RST HDMI_SC
L
FHDMI_N_IN
T
HSWI2C_ON HDMI_PO
N
HSW_PON
C B 8 2
5 2 0 4 5
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
R84
7
100
1000P(B)
C80
4
TP753
+ 3 . 3 S
R
755
10
K
D G N D
R75
6
no_use
R76
4
4.7
K
D
GND
+ 3 . 3 M
D G N D
C 8 3 3
0 . 1 / 1 0 ( B J )
C 7 6 1
1 0 0 0 P ( B )
J 7 5 2
n o _ u s e
0
J 7 5 1
DV_PON DV_PON DV_PON
10
0
R78
7
C85
2
1000P(B)
D G N D
R 7 9 1
R 7 9 3
+ 3 . 3 M
C
7
8
0
R79
2
C
7
7
4
C
7
7
8
C77
6
I C 8 9
1
EN
2
C1
+
3 4 5 6 7 8
1 1 0 1 9 4 1 3 1 2 1 6 1 5 1
CB7
5
VB3899
0
1 2 3
C
7
7
9
C
7
7
7
D G N D
R 7 9 4
R78
9
+ 3 . 3 M
D G N D
R80
5
33X
4
R82
0
33X
4
+3.3
M
DGN
D
C78
4
0.1/10(BJ)
R81
4
33X
4
R81
7
33X
4
R81
0
33X
4
R81
2
33X
4
R 8 1 5
2 2 0 K X 4
R 8 1 8
2 2 0 K X 4
+ 3 . 3 M
D G N D
C85
3
0.1/10(BJ)
+ 3 . 3 M
IC88
TC74VHC273FT
1
C L R
2
Q 1
3
D 1
4
D 2
5
Q 2
6
Q 3
7
D 3
8
D 4
9
Q 4
1
0
G N D
1
1 C K
1
2 Q 5
1
3 D 5
1
4 D 6
1
5 Q 6
16
Q 7
17
D 7
18
D 8
19
Q 8
20
V C C
R 7 7 8
1 0 0 X 4
R 7 8 0
1 0 0 X 4
R 7 6 2
1 0 0 X 4
DGND
DGND
IC83
TC74VHC273FT
1
C L R
2
Q 1
3
D 1
4
D 2
5
Q 2
6
Q 3
7
D 3
8
D 4
9
Q 4
1
0
G N D
1
1 C K
1
2 Q 5
1
3 D 5
1
4 D 6
1
5 Q 6
16
Q 7
17
D 7
18
D 8
19
Q 8
20
V C C
DGND
DGND
R 7 6 6
1 0 0 X 4
C 7 7 0
0 . 1 / 1 0 ( B J )
C 7 6 8
0 . 1 / 1 0 ( B J )
+ 3 . 3 M
I C 8 0
T C 7 4 L C X 3 2 F T
9
1 0
8
I C 8 0
T C 7 4 L C X 3 2 F T
1 2
1 3
1 1
IC8
0
4 1 + V
R 7 8 6
3 3
IC8
0
7 - V
R 7 8 8
3 3
I C 8 0
T C 7 4 L C X 3 2 F T
1
2
3
D G N D
+ 3 . 3 M
I C 8 0
T C 7 4 L C X 3 2 F T
4
5
6
C77
3
0.1/10(BJ)
D G N D
R81
9
33
DGN
D
+ 3 . 3 M
R 8 2 1
1 M
0.1/10(BJ)
C 8 5 7
0
J75
0
R82
4
33X
4
1K
R82
8
R82
9
47K
+ 3 . 3 D S P
+ 3 . 3 M
D G N D
R 8 3 0
1 0 K
T P 8 3 7
T P 8 3 6
C B 7 7
n o _ u s e
1
2
1 4
1 3
3
4
5
6
7
8
9
1 0
1 1
1 2
+ 3 . 3 M
T P 8 4 6
T P 8 4 5
T P 8 4 4
IC7
7
5
D75
3
1SS355VM
+ 3 . 3 M
D75
2
1SS355VM
IC7
7
3
D G N D
R 8 4 4
0
+ 3 . 3 M
D 7 5 1
1 S S 3 5 5 V M
R84
2
470
K
D 7 5 4
R B 5 2 1 S - 3 0 T E 6 1
R 8 4 3
1 M
C86
7
0.1/10(BJ)
+ 3 . 3 M
I C 7 7
S N 7 4 L V C 1 G 1 7 D C K R
2 4
D G N D
C 8 6 8
1 0 / 1 0
R86
4
10K
D G N D
R 8 6 9
4 7 X 4
R 8 7 0
4 7 X 4
R85
1
100KX4
+ 3 . 3 M
+ 3 . 3 M
D G N D
R 3 1 1 6 N 2 7 1 A - T R - F
I C 9 4
1
O U T
2
V D D
3
G N D
4
N C
5
C D
C 8 7 0
0 . 1 / 1 0 ( B J )
C 8 6 9
0 . 0 1 5 / 1 6 ( B )
R 8 3 2
3 3 X 4
R 8 3 3
3 3
R 8 3 7
3 3 X 4
+ 3 . 3 M
D G N D
C 8 5 9
0 . 1 / 1 0 ( B J )
1 0 0 P ( C H )
C 8 6 5
D G N D
C 8 6 4
0 . 1 / 1 0 ( B J )
D G N D
+ 3 . 3 M
R
836
100K
R838
1
00K
D G N D
1 6 7 Q
R L T B U 6 7 5 1 A
4 . 7 K
R 8 4 0
C866
1/25
R 8 4 1
4 7 0
100K
R839
+ 3 . 3 M
C858
1/25
D G N D
C 8 6 0 1 0 0 P ( C H )
C 8 6 1 1 0 0 P ( C H )
C 8 6 2 1 0 0 0 P ( B )
C 8 6 3 1 0 0 0 P ( B )
D
GND
C787
0.1/10(BJ
)
+ 3 . 3 M
D G N D
R813
33
R
816
33
R809 33X4 R811 33X4
C785
0.1/10(BJ
)
+3.3
M
D
GND
R 8 0 0
3 3 X 4
R 8 0 1
3 3 X 4
R 8 0 2
3 3 X 4
R 8 0 3
3 3 X 4
D G N D
C 7 8 1
0 . 1 / 1 0 ( B J )
+ 3 . 3 M
D G N D
C 7 8 2
0 . 1 / 1 0 ( B J )
+ 3 . 3 M
D G N D
C 7 8 3
0 . 1 / 1 0 ( B J )
+ 3 . 3 M
R806
33
R807
33
R 7 9 8
3 3
R 7 9 5
3 3 X 4
R79
9
33X
4
R834
33
R 7 9 7 n o _ u s e
R 8 3 5
3 3 X 4
R 7 9 6
1 0 0 K
D G N D
T P 7 5 7
T P 7 5 6
D G N D
1 K
R 8 2 2
C85
6
no_use
T P 8 3 3
R 7 8 5
1 M
R 7 6 1
1 M
R 7 5 8
1 0 K
DACZ2_PO
N
DACZ2_N_MT RM
-
ADT_N_EN DIR_N_RST +3.3D_PO
N
DC_TRG
1
NPDA_SEL NPSEL_N_OE PR
Y
DIR1_N_CS USB_VBUS_PON DSP_MOSI DAC_PO
N
ADT_SE
L
DSP_SC
K
DSP_MISO ACPWR_DE
T
DIR1_N_INT RM
+
MCPU_N_RST TEST
DSP2_N_RST DSP2_N_C
S
DSP2_N_SPIRDY
NCPU_MOS
I
NCPU_PHOLD NCPU_PON DSP_PO
N
NCPU_N_RST NCPU_SPI_N_CS NCPU_MIS
O
NCPU_AMUTE NCPU_SPI_SCK NCPU_N_INT USB_VBUS_PRT NCPU_VBUSDRV NCPU_SPI_MOSI NCPU_SPI_MISO
C E C
C B 8 0
P H I
V B 3 9 0 7 0
1 2 3 4 5 6 7 8 9
10
C B 7 6
5 2 0 4 4
V Q 0 4 4 7 0
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
THM4
R 8 7 2
3 3 X 4
C 8 5 4
0 . 1 / 1 0 ( B J )
D G N D
C87
1
10/16
D G N D
NCPU_ADT_MUTE
R90
4
10
0
9 7 B C
I H P
0 9 9 8 3 B V
1 2 3
R90
0
1K
+ 3 . 3 D S P
0 J754
0
J
756
R 8 6 0
3 3 0
R
865
2.2K
0
J 7 5 8
J75
7
no_use
+ 3 . 3 M
R850 10
K
C750
1000P(B)
1 0 0
R 7 5 7
HDMI_PO
N
C 7 8 6
1 / 2 5
C78
8
1/2
5
C85
5
1/2
5
DSP_NIC
X L 7 5
1 2 M H Z
1
2
3
IC8
2
M 9 5 5 1 2 - R D W 6 T P / K
1
S
2
Q
3
W
4
V S S
5
D
6
C
7
H O L D
8
V C C
D 8 0 1
R B 5 0 0 V - 4 0
R 8 2 3
2 7 K
+ 3 . 3 M
R
873
220K
C800
10/10
D G N D
R P 1 3 0 K 3 3 1 D - T R
Y G 8 8 3 A 0
I C 8 4
4
V D D
3
C E / C E
1
V O U T
2
G N D
G
R P 1 3 0 K 3 3 1 D - T R
Y G 8 8 3 A 0
I C 8 5
4
V D D
3
C E / C E
1
V O U T
2
G N D
G
I C 8 7
n o _ u s e
1
V i n
2
E N
3
V o u t
4
G N D
T P 8 6 7
D G N D
C 8 7 2
n o _ u s e
C 8 7 3
n o _ u s e
D G N D
I
C86
MX29LV640EBTI-
7
5
1
4
1
3
1
2
1
1
1
0
1
9
8
7
6
5
4
3
2
1
3
2
2
2
1
2
0
2
9
1
8
1
7
1
6
1
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
I C 9 0
T M P M 4 6 2 F 1 5 F G ( A D
Y H 6 9 1 A 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
8 4
8 3
8 2
8 1
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
6 5
96 97 98 99
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
11
0
11
1
11
2
11
3
11
4
11
5
11
6
11
7
11
8
11
9
12
0
1 3 6
1 3 7
1 3 8
1 3 9
1 4 0
1 4 1
1 4 2
1 4 3
1 4 4
1 4 5
1 4 6
1 4 7
1 4 8
1 4 9
1 5 0
1 5 1
1 5 2
1 5 3
1 5 4
1 5 5
1 5 6
1 5 7
1 5 8
1 5 9
1 6 0
26 27 28 29 30 31
6 6
6 7
6 8
6 9
7 0
7 1
7 2
1 6 1
1 6 2
1 6 3
1 6 4
1 3 3
1 3 4
1 3 5
32
89 90 91 92 93 94 95
33 34 35 36 37 38 39 40
7 3
7 4
7 5
7 6
7 7
7 8
7 9
8 0
12
1
12
2
12
3
12
4
12
5
12
6
12
7
12
8
1 6 5
1 6 6
1 6 7
1 6 8
1 6 9
1 7 0
1 7 1
1 7 2
41 42 43 44
8 5
8 6
8 7
8 8
12
9
13
0
13
1
13
2
1 7 3
1 7 4
1 7 5
1 7 6
XL7
6
n o _ u s e
+ 3 . 3 M
1 0 0 P ( C H )
C 8 7 4
D
GND
D G N D
1000P(B
)
C80
5
Z o n e 2
S u r . B a c k
S u r r o u n d /
S u b w o o f e r
M a i n Z o n e
( 5 C H )
t o O P E ( 1 1 )
R S - 2 3 2 C
AUD_DE
T
THM
1
PS3_PR
T
TES
T
AMP_OL
V
MOD
E
FLD_N_RS
T
FLD_MOS
I
MIC_N_DE
T
FLD_N_C
S
T H M
E E P R O M
t o M A I N ( 1 )
+ 3 . 3 M
to 003.sh
t
(FPGA
)
+ 3 . 3 S
MODE
L
t o O P E ( 2 )
4
M
H
T
T
R
P
_
C
D
THM
2
THM
3
PS2_PR
T
PS1_PR
T
STBY_LE
D
t o O P E ( 1 )
FLD_PO
N
KY_AD1 VDL_RA PSW_DE
T
FLD_SC
K
REM_IN
1
RM
-
KY_AD2 DGN
D
ISEL_R
A
RM
+
DGN
D
+5.
6
+5.
6
+3.3
M
VDL_RB DGN
D
ISEL_R
B
PD_LED
USB_VBUS_PR
T
MODE
L
A 8 6 0 o n l y
3 . 0 V 0 . 3 V
t o 0 0 7 . s h t
( D I R & D A C ) t o 0 0 6 . s h t
( D S P )
t o 0 0 1 . s h t
( H D M I R x T X )
t o 0 0 5 . s h t
( N e t / U S B ) t o 0 0 2 . s h t
( V D e c ) t o 0 0 3 . s h t
( F P G A )
PS2_PR
T
I C / C B / X L : 7 5 - 9 9
O H T E R : 7 5 0 - 9 9 9
S h e e t 4 : u - C o m
M X I C B l a n k : X 9 6 9 7 B 0 M X 2 9 L V 6 4 0 E B T I - 7 0 G
E O N B l a n k : Y C 0 7 9 B 0 E N 2 9 L V 6 4 0 A B - 9 0 T I P
S T M i c r o Y D 8 5 3 A 0 M 9 5 5 1 2 - R D W 6 T P / K
R e n e s a s Y D 3 5 5 B 0 R 1 E X 2 5 5 1 2 A T A 0 0 I
( 2 1 2 5 )
(0.5%)
(0.5%
)
W r i t t e n b y Y E M : Y H 6 9 2 * 0
AUDIO_DE
T
R_200_DE
T
SP_IMP PS2_PR
T
PS1_PR
T
AMP_LM
T
AMP_OL
V
I_PR
T
DC_PRT VOL_SC
K
MG VOL_MOS
I
SPRY_5C
H
MUTE_H
P
SPRY_Z
2
THM3_PR
T
MUTE_S
B
MUTE_Z
2
MUTE_S
W
MUTE_5C
H
HP_N_DE
T
SPRY_S
B
TU_SDA TU_SCL TUN_N_IN
T
TU_N_RS
T
VID_SD
A
VID_SC
L
PS2_PR
T
VID_PO
N
VE VE VE ADCVBS AD
Y
+3.3
V
ADP
b
ADP
r
+3.3DS
P
DGN
D
THM
1
THM
2
t o M A I N ( 1 )
t o 0 0 2 . s h t
( V D e c )
S T M i c r o Y D 8 5 3 B 0 M 9 5 5 1 2 - R D W 6 T P / K
FLP_PO
N
HWDET
232C_T
X
232C_R
X
DGN
D
SC8RXD SC8SCK SC8TXD
D9 X1
D13
D7
CS3
D8
REGOUT
3
D0 D3
PM9
RVS
S
D11 SWV D15 PF2 PM6 PM7
PM1
0
PF1
DVS
S
DVS
S
TB5OUT
REGOUT
1
D5
PM8
DVDD3 RVDD3
D12
D1 X2 D2
D14
D6
REGIN1
DVS
S
D10
D4
TB7IN0
SWCLK DVDD3 SWDIO
D - F F 1 1
D - F F 2 1
P E 7
M O D E
X T 1
A V D D 3
P M 1 1
P E 6
S C 0 T X D
D V S S
S C 1 R X D
P F 8
S C 0 R X D
D V D D 3
P N 1
R E S E T
D V S S
P F 9
P F 1 0
P F 1 1
I N T 8
C E C
D V D D 3
I N T A
P G 1
P G 4
P G 5
P G 6
P G 7
P G 8
P G 9
P G 1 0
I N T 9
P G 0
S C 6 R X D
T B 9 I N 0
P G 2
P G 3
P N 0
N M I
P E 5
S C 6 T X D
X T 2
S C 6 S C K
T B 3 I N 0
S C 1 T X D
R E S E T
+ 3 . 3 M
to ICE & Flash Programmer
S W D I O
R X D
S W C L K
T X D
S W V
B O O T
R e s e t D e l a y 7 0 m s e c
S u r . B a c k
VREFH PH14 PL
3
PH13 AIN4 INTD A2 PH
5
DVSS A1 PH
6
AIN2 TBCIN0 A4 PH
7
PH
8
A7 PJ
0
A6 RVDD3 PN
4
RVSS A0 REGIN2 A3 REGOUT2 A5 PL
1
PH10 SC9SCK AIN1 INTF I2C3SDA AIN3 SC9TXD PH11 AIN0 INTE PH
9
DVDD3 AVSS PH12 I2C2SDA I2C2SCL
A 1 6
A 1 4
A 1 9
T E S T
P K 7
S C 7 R X D
A 9
A 1 0
A 1 1
D V D D 3
I 2 C 3 S C L
P B 8
D V S S
D V S S
P B 9
A 2 2
P K 1
C S 0
P K 2
P K 0
P K 3
W R
A 1 2
R D
P K 6
S C 7 S C K
A 2 1
A 2 0
A 2 3
A 1 7
A 1 3
D V S S
I 2 C 4 S D A
B O O T
A 1 8
I 2 C 4 S C L
C S 1
A 1 5
D V D D 3
I N T B
A 8
D V D D 3
C S 2
S C 7 T X D
D - F F 1 2
D - F F 2 2
D I A G _ C H E C K
HW_DET
MUTE_P_S
B
A 1 6
D Q 7
D Q 3
A 3
O E
R E S E T
A 2 0 D Q 1 2
W P / A C C
A 5
D Q 6
D Q 1
A 1 7
D Q 5
W E
A 1 0 D Q 1 4
A 1 1
A 1 5
V C C
D Q 0
A 8
A 6
A 1 9
D Q 1 3
D Q 8
D Q 9
D Q 1 0
A 2
D Q 2
A 2 1
V S S
A 4
D Q 4
A 1 3
A 1 2
A 0
A 1 8
A 7
D Q 1 1
D Q 1 5
B Y T E
R Y / B Y
A 9
A 1
C E
V S S
A 1 4
(1005)
(1005)
S O C K E T : W J 1 4 6 7 0 9 8 0 0 2 0 - 4 8 - P 1
n o u s e
IC79, 81, 83, 88 : TC74VHC273FT (EL,K)
Octal D-type flip-flop with clear
1 CLR
Q1
Q2
Q3
Q4
GND
D1
D2
D3
D4
2
3
4
5
6
7
8
9
10
D CK CLR
L
H
H
H
X X
L
H
X
1
11
3
2
D R
CK Q
D1
Q1
CLR
CK
Q
L
L
H
Qn
Inputs Output
Function
Clear
−
−
No Change
20 VCC
Q8
Q7
Q6
Q5
CK
D8
D7
D6
D5
19
18
17
16
15
14
13
12
11
4
5
D R
CK Q
D2
Q2
7
6
D R
CK Q
D3
Q3
8
9
D R
CK Q
D4
Q4
13
12
D R
CK Q
D5
Q5
14
15
D R
CK Q
D6
Q6
17
16
D R
CK Q
D7
Q7
18
19
D R
CK Q
D8
Q8
IC93: TC7WH126FU
Dual bus buffer
1 G1
2 A1
3 Y2
4 GND
8 Vcc
7 G2
6 Y1
5 A2
A
L
L
H
H
L
L
L
H H
H
L
H
B Y
1
3
2
5
4
GND
V
CC
IC91: TC7SH86FU
Exclusive OR gate
IN A
IN B
OUT Y
IC76, 78: SN74LV4051APWR
8-channel analog multiplexers/demultiplexers
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
COM
INH
C
B
A
11
10
9
6
3
13
14
15
12
1
5
2
4
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11 Y4
Y6
COM
Y7
Y5
INH
GND
GND
V
CC
Y2
Y1
Y0
Y3
A
B
C
INPUTS ON
CHANNEL
INH
L
L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
X
C
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
L
Y1
Y2
Y3
Y4
Y5
Y6
Y7
None
Y0
B A
IC77, 92 : SN74LVC1G17DCKR
Single schmitt-trigger buffer
1
2
3
5
4
NC
A
GND
VCC
Y
INPUT
A
OUTPUT
Y
L
H
L
H
IC80: TC74LCX32FT
Low voltage quad 2
input OR gate
with 5 V tolerant Inputs and outputs
Vcc 14
4B 13
4A 12
4Y 11
3B 10
3A 9
3Y 8
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
IC94 : R3116N271A-TR-F
Voltage detecter
V
DD
2
3
GND
C
D
5
Delay
Circuit
Vref
1
OUT
Pin No.
1
2
3
4
5
Symbol
GND
OUT
NC
V
DD
C
D
Description
Output Pin (“L” at Detection, “Hi-Z” at Released)
Ground Pin
Connecting Pin for External Capacitor for Output Delay
No Connection
Input Pin
IC82: M95512-RDW6TP/K
512 Kbit serial SPI bus EEPROM
HOLD
S
W Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
Data
Register
1 Page
X Decoder
Y Decoder
C
D
Q
Size of the
Read only
EEPROM
area
Status
Register
IC86: MX29LV640EBTI-7
64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V
IC90: TMPM462F15FG
CMOS 32-Bit Microcontroller
Cortex-M4F
NVIC
Debug
FLASH
1.5MB
or
1.0MB
RAM
192KB
BOOT
ROM
4KB
TMRB
SIO/UART
(16ch)
PORT
ADC
(20ch)
LVD
WDT
CG
EHOSC
IHOSC
IO Bus
X1
X2
ELOSC
XT1
XT2
APB
EBIF
RTC
Backup
RAM
1KB
UART
(2ch)
I2C
(5ch)
MPT
(2ch)
RMC
OFD
IHOSC
AHB to IO
Bridge
AHB to APB
Bridge
CEC
(6ch)
DMA
AHB-Lite
(unit A,B,C)
SSP
(3ch)
AHB Lite (max 120MHz)
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER FLASH
ARRAY
R
E
D
O
C
E
D-
X
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y-
DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
A0-AM
AM: MSB address
CE#
OE#
WE#
RESET#
BYTE#
WP#/ACC
DD
CE
Vref
1 4
2 3
Current Limit
V
OUT
GND
Pin No.
1
2
3
4
Symbol
V
OUT
GND
CE
V
DD
Description
Output Pin
Ground Pin
Chip Enable ("H" Active)
Input Pin
IC84, 85: RP130K331D-TR
Voltage regulator
MICROPROCESSOR
No replacement part available.
to DIGITAL 3/7
to DIGITAL 1/7 to DIGITAL 2/7 to DIGITAL 3/7 to DIGITAL 5/7 to DIGITAL 6/7 to DIGITAL 7/7
to DIGITAL 2/7
DIGITAL (1)
RESISTOR
REMARKS
NO MARK PARTS NAME
CARBON
CARBON
METAL
METAL
METAL
FIRE
CEMENT
SEMI
FILM RESISTOR
FILM RESISTOR
OXIDE FILM RESISTOR
FILM RESISTOR
PLATE RESISTOR
PROOF CARBON FILM RESISTOR
MOLDED RESISTOR
VARIABLE RESISTOR
(P=5)
(P=10)
CHIP RESISTOR
REMARKS
CAPACITOR
PARTS NAME
NO
NO
MARK
MARK
ELECTROLYTIC CAPACITOR
CERAMIC CAPACITOR
POLYESTER FILM CAPACITOR
POLYSTYRENE FILM CAPACITOR
MICA CAPACITOR
POLYPROPYLENE
FILM CAPACITOR
SEMICONDUCTIVE CERAMIC CAPACITOR
P
TANTALUM CAPACITOR
TUBULAR
S
CAPACITOR CERAMIC
FILM SULFIDE POLYPHENYLENE
CAPACITOR
N O T I C E
U.S.A
G
CANADA
STANDARD
L
CHINA
AUSTRALIA
SINGAPORE
KOREA
GENERAL
U
C
T
A
K
R
JAPAN
(model)
B BRITISH
J
SOUTH EUROPE E
V
TAIWAN
F RUSSIAN
P LATIN AMERICA
S BRAZIL
H THAI
Page 119 F9
to OPERATION (2)_CB344
(RX-V681)
Page 122 F9
to OPERATION (2)_CB344
(RX-A760)
Page 118 G8
to OPERATION (1)_CB303
(RX-V681)
Page 121 E9
to OPERATION (1)_CB304
(RX-A760)
Page 124 J6
to MAIN (1)_W108
Page 125 K7
to MAIN (1)_W109
Page 124 K7
to MAIN (3)_W112
3.300V
3.296V
0.001V 5.538V 5.538V 0.000V 0.000V 3.299V 3.221V 0.000V 0.000V 3.296V 3.269V 3.299V 3.177V
2.904V 3.272V 0.000V
2.871V 2.619V
2.790V 2.343V 2.622V 2.791V 3.115V 0.002V 3.205V 0.002V
0.000V 0.000V 0.000V
0.663V 0.000V 3.294V 3.296V 1.480V 2.059V 0.000V
3.299V 3.299V 3.298V 0.414V 3.276V 3.279V 2.059V
3.296V 0.000V 0.000V 0.000V 0.000V 3.300V 0.000V 0.000V 0.000V
0.000V 0.000V 0.000V
3.295V 0.022V 3.260V
3.282V 2.071V 3.282V 0.000V 3.202V 0.000V 3.290V 3.294V 0.000V 0.020V 3.282V 3.296V 3.289V
3.296V
3.294V
0.000V
3.292V
DIGITAL 4/7
Details of colored lines
Red / full line: Power supply (+)
Red /dashed line: Power supply (-)
Orange:
Signal detect
Yellow: Clock
Green: Protection detect
Brown: Reset signal
Blue: Panel key input
★
All voltages are measured with a 10M
Ω
/V DC electronic voltmeter.
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
RX-V681 RX-A760