Yamaha RX-V463, Service Manual

Page: 64 / 122

2
A B C D E F G H I J
1
3
4
5
7
RX-V463/HTR-6140/DSP-AX463
6
64
MICROPROCESSOR
IC41
AD91089Z
HDMI
Rx
IC12
ADV7441A
SPORT0
Tx
TSCLK0
TFS0
DT0PRI
DT0SEC
SPORT1
Tx
TSCLK1
TFS1
DT1PRI
DT1SEC
SPORT0
Rx
RSCLK0
RFS0
DR0PRI
DR0SEC
24.576MHz
ADC
IC39
PCM1803DBR
XM DT
IC36
F2621E
DIR
IC31
LC89057W
RX5
RX1
RX3
RX4
RX OUT
SDIN
DOUT
RMCK
HDMI
Tx
IC11
AD9389B
RBCK
RLRCK
RDATA
SCKI
BCK
LRCK
SBCK
SLRCK
256fs
64fs
fs
128fs
2fs
OCLK
SCLK
LRCLK
DATA
MCLKOUT
SCLK
LRCLK
I2S[0]
I2S[1]
I2S[2]
I2S[3]
SPDIF
MCLKOUT
SCLK
LRCLK
I2S[0]
I2S[1]
I2S[2]
I2S[3]
Optical Out
Coaxial In
Optical In1
Optical In2
DAC
IC38
PCM1680
To MAIN P.C.B.
DATA1
SCK
BCK
LRCK
SPORT1
Rx
RSCLK1
RFS1
DR1PRI
DR1SEC
Clock for DTS96/24
Master Clock
Bit Clock
Word Clock
Serial Data
IC33
TC74VHC157FT
IC44
TC74VHC153FT
IC43
TC74VHC153FT
IC34
TC74VHC157FT
AUDIO_CLK_SEL
AUDIO_SEL_A
AUDIO_SEL_B
AUDIO_SEL_A
AUDIO_SEL_B
SEL
SEL
AUDIO_DIRECT_ON
DASBL/DASBR
DASL/DASR
DAC/DASW
DAFL/DAFR
Direct Through Pass
DATA2
DATA3
DATA4
0
1
2
3
0
1
2
3
A B
A B
0
1
2
3
0
1
2
3
A
B
A
B
A
B
A
B
A
B
A
B
SPDIF
AUDIO_SEL
DIR 0
A B
1
0
1
0
0
1
1
XM
HDMI (I2S)
AUDIO_CLK_SEL
A (normal) 0
1
(default)
B (DTS96/24)
(default)
AUDIO_DIRECT_ON
A (Microprocessor) 0
1
B (direct through)
(default)
(512fs for DTS96/24)
USB Host
IC71
ISP1760
EBIU
D[0:16]
16,15
22,21
19,20
27,26
DSP
• See page 85-92
→
SCHEMATIC DIAGRAM
DSP CONTROL SECTION BLOCK DIAGRAM