PSR-A1000
13
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
MD1
MD2
Vcc (RTC)
XTAL2
EXTAL2
Vss (RTC)
NMI
IRQ0/IRL0/PTH[0]
IRQ1/IRL1/PTH[1]
IRQ2/IRL2/PTH[2]
IRQ3/IRL3/PTH[3]
IRQ4/PTH[4]
D31/PTB[7]
D30/PTB[6]
D29/PTB[5]
D28/PTB[4]
D27/PTB[3]
D26/PTB[2]
Vss
D25/PTB[1]
Vcc
D24/PTB[0]
D23/PTA[7]
D22/PTA[6]
D21/PTA[5]
D20/PTA[4]
Vss
D19/PTA[3]
Vcc
D18/PTA[2]
D17/PTA[1]
D16/PTA[0]
Vss
D15
Vcc
D14
D13
D12
D11
D10
D9
D8
D7
D6
Vss
D5
Vcc
D4
D3
D2
D1
D0
A0
A1
A2
A3
Vss
A4
Vcc
A5
A6
A7
A8
A9
A10
A11
A12
A13
Vss
A14
Vcc
A15
A16
A17
A18
A19
A20
A21
Vss
A22
Vcc
A23
Vss
A24
Vcc
A25
BS/PTK[4]
RD
WE0/DQMLL
WE1/DQMLU/WE
WE2/DQMUL/ICIORD/PTK[6]
WE3/DQMUU/ICIOWR/PTK[7]
RD/WR
PTE[7]
Vss
CS0
Vcc
CS2/PTK[0]
CS3/PTK[1]
CS4/PTK[2]
CS5/CE1A/PTK[3]
CS6/CE1B
CE2A/PTE[4]
CE2B/PTE[5]
I
I
-
I
O
-
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
I/O
I/O
O
O
O
O
-
O
-
O
O
O
O
O
O
O
O
O
-
O
-
O
O
O
O
O
O
O
-
O
-
O
-
O
-
O
I/O
O
O
O
I/O
I/O
O
I/O
-
O
-
I/O
I/O
I/O
I/O
O
I/O
I/O
System clock
Power supply (3.3 V)
Clock
Clock
Ground (0 V)
Interrupt request
Interrupt request
Interrupt request
Data bus/ I/O port B
Ground (0 V)
Interrupt request
Power supply (3.3 V)
Data bus/ I/O port B
Data bus/ I/O port A
Ground (0 V)
Data bus/ I/O port A
Power supply (3.3 V)
Data bus/ I/O port A
Ground (0 V)
Data bus
Power supply (3.3 V)
Data bus
Ground (0 V)
Data bus
Power supply (3.3 V)
Data bus
Address bus
Ground (0 V)
Address bus
Power supply (3.3 V)
Address bus
Ground (0 V)
Address bus
Power supply (3.3 V)
Address bus
Ground (0 V)
Address bus
Power supply (3.3 V)
Address bus
Ground (0 V)
Address bus
Power supply (3.3 V)
Address bus
Bus control/ I/O port K
Read strobe
Select signal/DQM (SDRAM)
Select signal/DQM (SDRAM)/PCMCIA WE
Select signal/DQM (SDRAM)/PCMCIA I/O read/ I/O port K
Select signal/DQM (SDRAM)/PCMCIA I/O write/ I/O port K
Read/Write signal
I/O port E
Ground (0 V)
Chip select
Power supply (3.3 V)
Chip select/ I/O port K
Chip select/ I/O port K
Chip select/ I/O port K
Chip select/CE1/ I/O port K
Chip select/CE1
Chip enable/ I/O port E
Chip enable/ I/O port E
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
CKE/PTK[5]
RAS3L/PTJ[0]
RAS2L/PTJ[1]
CASLL/CAS/PTJ[2]
Vss
CASLH/PTJ[3]
Vcc
CASHL/PTJ[4]
CASHH/PTJ[5]
DACK0/PTD[5]
DACK1/PTD[7]
CAS2L/PTE[6]
CAS2H/PTE[3]
RAS3U/PTE[2]
RAS2U/PTE[1]
PTE[0]
BACK
BREQ
WAIT
RESETM
PTH[5]/ADTRG
IOIS16/PTG[7]
PTG[6]
PTG[5]
PTG[4]
PTG[3]
PTG[2]
Vss
PTG[1]
Vcc
PTG[0]
PTF[7]/PINT[15]
PTF[6]/PINT[14]
PTF[5]/PINT[13]
PTF[4]/PINT[12]
PTF[3]/PINT[11]
PTF[2]/PINT[10]
PTF[1]/PINT[9]
PTF[0]/PINT[8]
MD0
Vcc (PLL1)
CAP1
Vss (PLL1)
Vss (PLL2)
CAP2
Vcc (PLL2)
PTH[6]
Vss
Vss
Vcc
XTAL
EXTAL
STATUS[0]/PTJ[6]
STATUS[1]/PTJ[7]
TCLK/PTH[7]
IRQOUT
Vss
CKIO
Vcc
TxD0/SCPT[0]
SCK0/SCPT[1]
TxD1/SCPT[2]
SCK1/SCPT[3]
TxD2/SCPT[4]
SCK2/SCPT[5]
RTS2/SCPT[6]
RxD0/SCPT[0]
RxD1/SCPT[2]
Vss
RxD2/SCPT[4]
Vcc
CTS2/IRQ5/SCPT[7]
PTC[7]/PINT[7]
PTC[6]/PINT[6]
PTC[5]/PINT[5]
PTC[4]/PINT[4]
Vss
WAKEUP/PTD[3]
Vcc
PTD[2]/RESETOUT
PTC[3]/PINT[3]
PTC[2]/PINT[2]
PTC[1]/PINT[1]
PTC[0]/PINT[0]
DRAK0/PTD[1]
DRAK1/PTD[0]
DREQ0/PTD[4]
DREQ1/PTD[6]
RESETP
CA
MD3
MD4
MD5
AVss
AN[0]/PTL[0]
AN[1]/PTL[1]
AN[2]/PTL[2]
AN[3]/PTL[3]
AN[4]/PTL[4]
AN[5]/PTL[5]
AVcc
AN[6]/DA[1]/PTL[6]
AN[7]/DA[0]/PTL[7]
AVss
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
-
I
-
I
I
I
I
I
I
I
I
I
I
-
-
-
-
-
-
I
-
-
-
O
I
I/O
I/O
I/O
O
-
I/O
-
O
I/O
O
I/O
I/O
I
-
I
-
I
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
-
I
I
I
I
I
I
-
I/O
I/O
-
CK enable (SDRAM)/ I/O port K
RAS/ I/O port J
RAS/ I/O port J
CAS (DRAM)/CAS (SDRAM)/ I/O port J
Ground (0 V)
CAS (DRAM)/ I/O port J
Power supply (3.3 V)
CAS (DRAM)/ I/O port J
CAS (DRAM)/ I/O port J
DMAC/ I/O port D
DMAC/ I/O port D
CAS (DRAM)/ I/O port E
CAS (DRAM)/ I/O port E
RAS/ I/O port E
RAS/ I/O port E
I/O port E
System clock
System clock
Bus control
Reset
I/O port H/Analog
Right protect/Input port G
I/O port G
Ground (0 V)
I/O port G
Power supply (3.3 V)
I/O port G
I/O port F/Port Interrupt request
System clock
Power supply (3.3 V)
Clock
Ground (0 V)
Ground (0 V)
Clock
Power supply (3.3 V)
I/O port H
Ground (0 V)
Ground (0 V)
Power supply (3.3 V)
Clock
Clock
System clock
Timer
Interrupt request
Ground (0 V)
Clock
Power supply (3.3 V)
Forward data/Output port for SCI
Serial clock/ I/O port for SCI
Forward data/Output port for SCI
Serial clock/ I/O port for SCI
Transmit request/ I/O port for SCI
Reception data/Input port for SCI
Ground (0 V)
Reception data/Input port for SCI
Power supply (3.3 V)
Transmit clear/Interrupt request/Input port for SCI
I/O port C/Interrupt request
Ground (0 V)
Interrupt request/ I/O port D
Power supply (3.3 V)
I/O port D/Reset
I/O port C/Interrupt request
DMA request/ I/O port D
DMA request/ I/O port D
DMA request/ I/O port D
DMA request/ I/O port D
System clock
System clock
System clock
System clock
System clock
Analog ground (0 V)
A/D change input/Input port L
Analog power supply (3.3 V)
A/D change input/D/A change output/Input port L
Analog ground (0 V)
HD6417709F80B (XV250B00) CPU
DM: IC100
