21
P5000S/P7000S
■
IC BLOCK DIAGRAM
（IC ブロック図）
• NJM2068MD-TE2
(X3505A00)
Dual Operational Amplifier
P5000S IN: IC301, IC302, IC303, IC304,
IC305, IC306, IC307
PAH: IC201
P7000S IN: IC301, IC302, IC303, IC304,
IC305, IC306, IC307
PAH: IC201
P5000S PS: IC402
P7000S PS: IC402
IR2110
(X2382A00)
DRIVER
SG3525AN
(X2383A00)
P5000S PS: IC401
P7000S PS: IC401
Regulating Pulse Width Modulator
1
2
3
4
-V
8
7
6
5
Output A
+V
Non-Inverting
Input A
-DC Voltage Supply
+DC Voltage
Supply
Output B
Inverting
Input B
Non-Inverting
Input B
Inverting
Input A
+
-
+
-
1
LO
2
3
4
5
6
7
COM
VCC
VS
VB
HO
9
10
11
12
13
14
VSS
LIN
SD
HIN
VDD
8
VDD/VCC
LEVEL
SHIFT
PULSE
GEN
PULSE
GEN
VDD
VSS
HIN
SD
LIN
10
9
11
12
13
R
S
Q
R
S
Q
VDD/VCC
LEVEL
SHIFT
HV
LEVEL
SHIFT
UV
DETECT
UV
DETECT
DELAY
PULSE
FILTER
R
R
S
Q
6
7
5
3
1
2
COM
LO
VCC
VS
VB
HO
INV. INPUTN
N.I. INPUT
SYNC
OSC. OUTPUT
C
T
R
T
DISCHARGE
SOFT-START
V
REF
+V
IN
V
C
GROUND
OUTPUT A
SHUTDOWN
COMPENSATION
OUTPUT B
OSCILLATOR
16
15
4
13
11
14
12
8
10
3
6
7
5
1
2
FLIP/
FLOP
REFERENCE
REGULATOR
E/A
B
A
5K
5K
50 A
PWM
9
1
INV. INPUTN
2
3
4
5
6
7
8
N.I. INPUT
SYNC
OSC. OUTPUT
C
T
R
T
DISCHARGE
SOFT-START
11
12
13
14
15
16
V
REF
+V
IN
OUTPUT B
V
C
GROUND
OUTPUT A
SHUTDOWN
COMPENSATION
9
10
