42
R-840/NS-BP300
R-840/NS-BP30
0
Pin
No.
Port Name
Function Name
(P.C.B.)
I/O
Detail of Function
P
o
w
erOn
Standb
y
MCUSleep
[Standb
y]
W
riting
1
P9_6/ANEX1/SOUT4
RDS_N_RST
O
O
O
RDS reset control
2
P9_5/ANEX0/CLK4
RDS_SCK
SO
O
O
Serial clock for RDS communication
3
P9_4/DA1/TB4IN
RDS_RDY
I
O
O
RDS READY input terminal
4
P9_3/DA0/TB3IN
FL_N_IC
O
O
O
FL initial clear control
5
P9_2/TB2IN/SOUT3
FL_SDT
SO
O
O
FL serial communication data
6
P9_1/TB1IN/SIN3
FL_N_CS
O
O
O
FL communication chip select
7
P9_0/TB0IN/CLK3
FL_SCK
SO
O
O
FL communication serial clock
8
BYTE
BYTE
MCU
MCU
MCU
Connect to Vss when using the single chip mode (for change of
external data bus width: 16bit)
9
CNVss
CNVss
MCU
MCU
MCU
Low: Processor mode select: Single chip mode
H: To flash included boot mode
10
P8_7/XCIN
XCIN
MCU
MCU
MCU
Sub clock 32.768 kHz input
11
P8_6/XCOUT
XCOUT
MCU
MCU
MCU
Sub clock 32.768 kHz output
12 RESET
N_RST
MCU
MCU
MCU
Reset input
13 Xout
XOUT
MCU
MCU
MCU
Main clock 20 MHz output
14 Vss
VSS
MCU
MCU
MCU
15 Xin
XIN
MCU
MCU
MCU
Main clock 20 MHz input
16 Vcc1
VCC1
MCU
MCU
MCU
17 P8_5/NMI/SD
/NMI
MCU
MCU
MCU
No use (Pull-up)
*
Nch Open Drain
18 P8_4/INT2/ZP
PWR_SW
IRQ
IRQ
O
POWER SW detection
19 P8_3/INT1
REM
IRQ
IRQ
O
Remote control pulse input
20 P8_2/INT0
IPD_DET
IRQ
IRQ
O
iPod detection
21 P8_1/TA4IN/U/CTS5/RTS5
HP_DET
I
O
O
Headphone detection
Hi: Insert HP
22 P8_0/TA4OUT/U//RXD5/SCL5
EEP_IP_SCL
SO
O
O
I2C bus clock for EEP ROM and iPod certification
23 P7_7/TA3IN/CLK5
IP_N_RST
O
O
O
iPod certification chip reset control
50kHz when in the I2C low speed mode
As inputting the high speed causes a malfunction, be sure to set at
“Low” and keep the reset state except during communication
24 P7_6/TA3OUT/TXD5/SDA5
EEP_IP_SDA
SIO
O
O
I2C bus data for EEP ROM and iPod certification
25 P7_5/TA2IN/W
NC
O
O
O
26 P7_4/TA2OUT/W
IPD_PON
O
O
O
Power supply regulator IC for iPod charge ON/OFF control
Hi = ON, Low = OFF
27 P7_3/CTS2/RTS2/TA1IN/V
IPD_ACC_EN
O
O
O
Set at Low while in the Standby mode and when AC turned off
Kept at Hi in the usual state (communicable with iPod)
28 P7_2/CLK2/TA1OUT/V
IPD_AP_DET
I
O
O
Accessory power detection
29 P7_1/RXD2/SCL2/TA0IN/TB5IN
IPD_MISO
SI
O
O
iPod UART communication
*
Nch Open Drain
30 P7_0/TXD2/SDA2/TA0OUT
IPD_MOSI
SO
O
O
iPod UART communication
*
Nch Open Drain
31 P6_7/TXD1/SDA1
WR_MOSI
SO
SO
O
MCU
For simple emulation
Rx during flash writing
32 P6_6/RXD1/SCL1
WR_MISO
SI
SI
O
MCU
For simple emulation
Tx during flash writing
33 P6_5/CLK1
WR_CLK
SO
SO
O
MCU
For simple emulation
Clock during flash writing
34 P6_4/CTS1/RTS1/CTS0/CLKS1
WR_BUSY
O
O
O
MCU
For simple emulation
BUSY output during flash writing
35 P6_3/TXD0/SDA0
DAB_SDA
SIO
O
O
Bus data of DAB I2C communication
I2C fs = 100 k/400 k
36 P6_2/RXD0/SCL0
DAB_SCL
SO
O
O
Bus clock of DAB I2C communication
I2C fs = 100 k/400 k
37 P6_1/CLK0
DAB_N_RST
O
O
O
DAB reset control
38 P6_0/CTS0/RTS0
NC
O
O
O
39 P5_7/RDY/CLKOUT
NC
O
O
O
40 P5_6/ALE
NC
O
O
O
41 P5_5/HOLD
/EMP
I
(LO) for flash writing
Pull down as the Hiz state may occur while the emulator is operating
Summary of Contents for NS-BP300
Page 5: ...5 R 840 NS BP300 R 840 NS BP300 B G models ...
Page 6: ...6 R 840 NS BP300 R 840 NS BP300 NS BP300 C T K A B G L V models ...
Page 7: ...7 R 840 NS BP300 R 840 NS BP300 REAR PANELS C model T model R 840 ...
Page 8: ...8 R 840 NS BP300 R 840 NS BP300 K model A model ...
Page 9: ...9 R 840 NS BP300 R 840 NS BP300 G model B model ...
Page 10: ...10 R 840 NS BP300 R 840 NS BP300 L model V model ...
Page 11: ...11 R 840 NS BP300 R 840 NS BP300 NS BP300 C T K A B G L V models C K A B G L V models T model ...
Page 48: ...48 R 840 NS BP300 R 840 NS BP300 MEMO ...
Page 83: ...83 R 840 NS BP300 R 840 NS BP300 MEMO ...
Page 84: ...R 840 NS BP300 ...
