Yamaha Mio, Service Manual

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Addressing the RAM
The MIO can access up to 1 Megabyte of RAM which takes 20 bits to address. Address bits A19-
A16 are set from writing to the latch at $D1E2, bits A15-A8 are set from writing to the latch at
$D1E0, and bits A7-A0 are CPU address lines A7-A0 when reading/writing $D6xx. Thus there are up
to 4096 "pages" of memory that may appear at the $D6xx window.
In order to access the memory, it must first be enabled by setting $D1E2 bit 5 to "1" (this also turns
on the MIO's red LED). It is generally a good idea to leave the RAM disabled while not using it in
case of a system crash (which could inadvertently write in the $D6xx window).
When power is removed from the computer (for whatever reason), the MIO will continue refreshing
its dynamic RAM. This is accomplished by its ability to maintain a 02 clock after the computers clock
has stopped. VC1 adjusts the MIO's 02 clock frequency. Adjustment requires special equipment and
should not be attempted.
Checking IRQ Status
The MIO has two sources of interrupts; one is the ACIA and the other is the parallel printer port. The
printer port may interrupt the computer only if bit 7 of $D1E2 is set ('1') and the printer BUSY is false
('0'). Bit 4 of $D1E3 is the general IRQ flag from the MIO (a 1 indicates that IRQ- is true). If bit 3 is
also set, then the IRQ- is caused by the printer. If not, then it must be the ACIA (in which case
$D1C1 bit 7 should be set).
Note that the parallel device IRQ mask (PDIMSK at $249) is set to $10 by the MIO RAM. This is
because, there is only one interrupt handler (which supports all possible MIO interrupts) in the ROM.
In fact, the system would crash if the OS tried to enter any of the other ROM banks to service the
IRQ.
Accessing the ROM
The ROM on the MIO contains all the software necessary to access the hard disk, the RAM, the
ACIA (as an R: or P:), and the parallel printer port. It also contains the configuration which is
downloaded into the computer RAM when RESET are pressed.
The ROM is accessed as 4-2K banks. (An additional 8K is reserved for the 80 column adapter.) Bits
5-2 (of $D1E3) select which bank will be active (if any) at the $D800-$DFFF region. Only 1 bit may
be set and its position selects which bank of ROM is active. If all bits are zero, then no banks are
active and the Floating Point Math package in the OS ROM is enabled.
According to Atari spec, 1 device is to occupy one bank of ROM and that device has a specific
address range legal to it at $D1xx. Since the MIO is an all inclusive device, however, it deviates from
this spec. Instead, it tries to cram as much code as possible into a small space. This meant juggling
the banks around to get along with the computer and to allow for expansion of an 80 column
adapter. This is why there is only one interrupt handler, yet several input bits are returned in what is
considered to be strictly an interrupt sense register (at $D1FF).
MIO Service Manual Page 62