Yamaha LSI YMF744B Technical Manual Download Page 18

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YMF744B

February 3, 1999

-18-

3Fh: Maximum Latency

Read Only
Default: 19h
Access Bus Width: 8, 16, 32-bit

Maximum Latency

b[7:0] ..........Maximum Latency

This register indicates how often DS-1S generates the Bus Master Request.

This register is hardwired to 19h.

40-41h: Legacy Audio Control

Read / Write
Default: 907Fh
Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

LAD

SIEN

MPUIRQ

SBIRQ

SDMA

I/O

MIEN

MEN

GPEN FMEN SBEN

b0................SBEN: Sound Blaster Enable

This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits,

when LAD is set to “0”. The FM Synthesizer registers can be accessed via SB I/O space, while the SB

block is enabled, even if FMEN is set to “0”.

“0”: Disable the mapping of the SB block to the I/O space

“1”: Enable the mapping of the SB block to the I/O space

(default)

b1................FMEN: FM Synthesizer Enable

This bit enables the mapping of the FM Synthesizer block in the I/O space specified by the FMIO bits,

when LAD is set to “0”. FM Synthesizer registers can be accessed via SB I/O space, while the SB block

is enabled, even if FMEN is set to “0”.

“0”: Disable the mapping of the FM Synthesizer block to the FMIO space

“1”: Enable the mapping of the FM Synthesizer block to the FMIO space

(default)

After setting FMEN to “1”, about 100 msec is necessary before accessing these I/O space.

b2................GPEN: Gameport Enable

This bit enables the mapping of the Joystick block in the I/O space specified by the JSIO bits, when LAD

is set to “0”.

“0”: Disable the mapping of the Joystick block

“1”: Enable the mapping of the Joystick block

(default)

b3................MEN: MPU401 Enable

This bit enables the mapping of the MPU401 block in the I/O space specified by the MPUIO bits, when

LAD is set to “0”.

“0”: Disable the mapping of the MPU401 block

“1”: Enable the mapping of the MPU401 block

(default)

Summary of Contents for LSI YMF744B

Page 1: ... to AC 97 which provides high quality DAC ADC and analog mixing and it can connect two AC 97s In addition it supports consumer IEC958 Audio Digital Interface SPDIF to connect external audio equipment by digital FEATURES PCI 2 2 Compliant PC 98 PC 99 specification Compliant PCI Bus Power Management rev 1 0 Compliant Support D0 D2 and D3 state Supports clock run PCI Bus Master for PCI Audio True Ful...

Page 2: ...ation Therefore it provides much more real world acoustic sound outputs fundamentally different from the Wavetable sound generator that simply processes the recorded acoustic sound sources only The SONDIUS XG adds the technology of virtual acoustic sound to the XG format 4 Sensaura Sensaura is a technology which provides 3D positional audio and moving effect by HRTF Head Related Transfer Function ...

Page 3: ...PERR SERR PAR CBE1 PVSS2 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD19 AD26 SPDIFIN TEST VSS3 VDD1 CSDO CBCLK CSDI0 CSYNC VDD2 CMCLK IRQ5 GPIO2 GPIO1 GPIO0 RESERVE8 RESERVE9 RESERVE10 VSS1 XI24 XO24 LOOPF SPDIFOUT ZVBCLK ZVLRCK ZVSDI PVSS1 CBE0 IRQ9 IRQ10 IRQ11 IRQ7 CVDD1 LVDD DOCKEN CSDI2 RESERVE3 RESERVE2 VSS2 VDD0 CRST RESERVE0 RESERVE13 RESERVE14 RESERVE15 RESERVE16 RESERVE12 RESERVE11 1 103 104 ...

Page 4: ... 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IRDY FRAME PVSS3 CBE2 AD17 AD18 AD19 AD20 AD21 AD22 PVSS4 AD23 IDSEL CBE3 TRDY PVDD1 STOP SERR PAR CBE1 PVSS2 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD16 AD24 PERR RST 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 102 100 99 98 97 101 AD25 PVDD2 AD26 AD27 AD28 PVSS5 AD29 AD30 GP6 GP7 RESERVE1 CVDD2 INTA...

Page 5: ...PCI Request PCGNT I P PC PCI Grant PERR IO Pstr Parity Error SERR O Pod System Error INTA O Pod Interrupt signal output for PCI bus SERIRQ IO Ptr Serialized IRQ CLKRUN IO Ptr Clock Run 2 AC 97 Interface 8 pin Name I O Type Size Function CRST O T 6mA Reset signal for AC 97 CMCLK O C 6mA Master Clock for AC 97 24 576MHz CBCLK I T AC link Bit Clock for AC 97 audio data CSDO O T 6mA AC link AC 97 Seri...

Page 6: ... Legacy Audio IRQ10 O Ttr 12mA Interrupt10 of Legacy Audio IRQ11 O Ttr 12mA Interrupt11 of Legacy Audio GP 3 0 I A Game Port GP 7 4 I Tup Game Port RXD I Tup MIDI Data Receive TXD O T 2mA MIDI Data Transfer 5 Miscellaneous 11 pin Name I O Type Size Function ROMCS O T 2mA Chip select for external EEPROM ROMSK VOLUP IO Tup 2mA Serial clock for external EEPROM or Hardware Volume Up ROMDO VOLDW IO Tup...

Page 7: ...r supply for Core logic VDD 2 0 3 3V Power supply VSS 3 0 Ground LVDD 3 3V Power supply for PLL Filter 7 Reserve Pin 13 pin Name I O Type Size Function RESERVE0 O Pod RESERVE 3 2 I Tup RESERVE 16 8 1 Reserve pins Do not connect externally TYPE T TTL A Analog Ptr Tri State PCI Ttr Tri State TTL C CMOS Pstr Sustained Tri Sate PCI Tup Pull up Max 300kohm TTL P PCI Pod Open Drain PCI ...

Page 8: ...g Register PCI Interface Legacy Audio FM Synthesizer SB Pro D DMA Engine MPU401 Joystick PCI Bus Master DMA Controller PCI Native Audio XG Synthesizer DirectSound Acc Wave In Out ZV Port SRC Sampling Converter SPDIF Output AC Link Interface Revision2 1 SPDIF Input Selector GPIO EEPROM I F ...

Page 9: ...erved 0 1 1 0 Memory Read 0 1 1 1 Memory Write 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 Configuration Read 1 0 1 1 Configuration Write 1 1 0 0 Memory Read Multiple not support 1 1 0 1 Dual Address Cycle not support 1 1 1 0 Memory Read Line not support 1 1 1 1 Memory Write and Invalidate not support DS 1S does not assert DEVSEL when accessed with commands that are indicated as not supported or res...

Page 10: ... 1Bh Legacy Audio I O Base Address Dummy for Joystick 1C 2Bh Reserved 2C 2Fh Subsystem ID Subsystem Vendor ID 30 33h Reserved 34 37h Reserved Cap Pointer 38 3Bh Reserved 3C 3Fh Maximum Latency Minimum Grant Interrupt Pin Interrupt Line 40 43h Extended Legacy Audio Control Legacy Audio Control 44 47h Subsystem ID Write Subsystem Vendor ID Write 48 4Bh DS 1S Power Control 1 DS 1S Control 4C 4Fh DS 1...

Page 11: ...evice ID of DS 1S This register is hardwired to 0010h 04 05h Command Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SER PER BME MS IOS b0 IOS I O Space This bit is a dummy one that is capable of writing This bit indicates for BIOS or OS that DS 1S includes I O devices b1 MS Memory Space This bit enables DS 1S to response to Memory Space ...

Page 12: ... ACPI Mode register ACPI bit is 0 the bit is 1 When ACPI bit is 1 the bit is 0 b8 DPD Data Parity Error Detected This bit indicates that DS 1S detects a Data Parity Error during a PCI master cycle b 10 9 DEVT DEVSEL Timing This bit indicates that the decoding speed of DS 1S is Medium b11 STA Signaled Target Abort This bit indicates that DS 1S terminates a transaction with Target Abort during a tar...

Page 13: ...egister indicates the programming interface of DS 1S This register is hardwired to 00h 0Ah Sub class Code Read Only Default 01h Access Bus Width 8 16 32 bit b7 b6 b5 b4 b3 b2 b1 b0 Sub class Code b 7 0 Sub class Code This register indicates the sub class of DS 1S This register is hardwired to 01h DS 1S belongs to the Audio Sub class 0Bh Base Class Code Read Only Default 04h Access Bus Width 8 16 3...

Page 14: ...indicates the device type of DS 1S This is hardwired to 00h 10 13h PCI Audio Memory Base Address Read Write Default 00000000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MBA b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 MBA higher b 31 15 MBA Memory Base Address This register indicates the physical Memory Base address of the PCI Audio regist...

Page 15: ...ister is a dummy one each for the I O addresses of the above blocks is assigned with the I O addresses set to 4C 4Dh and 60 65h respectively by the software driver 18 1Bh Legacy Audio I O Base Address Dummy for Joystick Read Write Default 00000001h Access Bus Width 8 16 32 bit b15 B14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IOBASE1 I O b31 B30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 ...

Page 16: ...ally Then Subsystem Vendor ID Write Register is invalid In case EEPROM is not externally the default value is the YAMAHA s Vendor ID 1073h 2E 2Fh Subsystem ID Read Only Default 0010h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem ID b 15 0 Subsystem ID This register contains the Subsystem ID In general this ID is used to distinguish adapters or systems...

Page 17: ...er and this register indicates 50h When ACPI bit is 1 this register indicates 00h 3Ch Interrupt Line Read Write Default 00h Access Bus Width 8 16 32 bit b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Line b 7 0 Interrupt Line This register indicates the interrupt channel that INTA is assigned to 3Dh Interrupt Pin Read Only Default 01h Access Bus Width 8 16 32 bit b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Pin b 7 0 Int...

Page 18: ...pping of the SB block to the I O space default b1 FMEN FM Synthesizer Enable This bit enables the mapping of the FM Synthesizer block in the I O space specified by the FMIO bits when LAD is set to 0 FM Synthesizer registers can be accessed via SB I O space while the SB block is enabled even if FMEN is set to 0 0 Disable the mapping of the FM Synthesizer block to the FMIO space 1 Enable the mapping...

Page 19: ...e I O address of each block 0 16 bit address decode 1 10 bit address decode default b 7 6 SDMA Sound Blaster DMA 8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block 0 DMA ch0 1 DMA ch1 default 2 reserved 3 DMA ch3 b 10 8 SBIRQ Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block 0 IRQ5 default 1 IRQ7 2 IRQ9 3 IRQ10 ...

Page 20: ...acy Audio block default When this bit is set to 1 DS 1S does not respond to the I O Target transaction for legacy I O address on the PCI bus 42 43h Extended Legacy Audio Control Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IMOD SBVER SMOD MAIM b8 MAIM MPU401 Acknowledge Interrupt Mask This bit determine whether interrupt is asserted wh...

Page 21: ...ets the Subsystem Vendor ID that is read from 2C 2Dh Subsystem Vendor ID register The default value is the YAMAHA Vendor ID 1073h IHVs must change this ID to their Vendor ID in the BIOS POST routine In case EEPROM connects externally this register is invalid and do not reflect to Subsystem Vendor ID 46 47h Subsystem ID Write Register Read Write Default 0010h Access Bus Width 16 bit b15 b14 b13 b12...

Page 22: ...ill automatically return to 0 after 1 3µs time duration This bit is valid only while the ACLS bit is set to 0 Except in this case even if this bit is attempted to be set to 1 no warm reset will be generated write operation of 1 remains disabled 0 Normal default 1 AC 97 Warm Reset b3 ACLS AC Link Status Read Only This bit indicates whether or not the AC link is active This bit is 1 when the AC link...

Page 23: ...ely after power on reset or hardware reset 0 Normal default 1 Resets the flip flop circuit following the analog comparator stage on the joystick port b8 PR0 AC 97 Power Down Control 0 This bit controls the power state of the ADC and Input Mux in the Primary AC 97 0 Normal default 1 Power down b9 PR1 AC 97 Power Down Control 1 This bit controls the power state of the DAC in the Primary AC 97 0 Norm...

Page 24: ...bit status of the power control register in the Primary AC 97 Respective data set to b 15 8 are correspondingly set into the Power down Control Status register in the Primary AC 97 via the AC Link These are not set into the power down register in the Secondary AC 97 4C 4Dh D DMA Slave Configuration Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b...

Page 25: ...efault 1 Disable b1 PSFM Power Save FM Synthesizer Setting this bit to 1 stops a clock supplied to the FM synthesizer block 0 Normal default 1 Disable b2 PSSB Power Save Sound Blaster Setting this bit to 1 stops a clock supplied to the Sound Blaster block 0 Normal default 1 Disable b3 PSMPU Power Save MPU401 Setting this bit to 1 stops a clock supplied to the MPU401 block 0 Normal default 1 Disabl...

Page 26: ...t to 1 stops a clock supplied to the DIR block 0 Normal default 1 Disable b10 PSACL Power Save AC Link Setting this bit to 1 stops a clock supplied to the AC Link block 0 Normal default 1 Disable b11 PSIO Power Save I O Pad Setting this bit to 1 fixes the levels of the I O pins except for the PCI interface and AC Link Output pins retain current level and any signals from input pins are ignored 0 N...

Page 27: ...t SPDIF in AC97 Master Clock MPU401 Joystick CMCD PSFM PSSB PSMPU PSJOY PSPCA PSSRC PSZV PSDIT PSDIR PSACL PSHWV Power Management Block 50h Capability ID Read Only Default 01h Access Bus Width 8 16 32 bit b7 b6 b5 b4 b3 b2 b1 b0 Capability ID b 7 0 Capability ID Capability Identifier This register indicates that the new capability register is for Power Management control This register is hardwired...

Page 28: ... the power state It is hardwired to 1 54 55h Power Management Control Status Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PS b 1 0 PS Power State These bits determine the power state of DS 1S DS 1S supports the following power states 0 D0 1 D1 not supported 2 D2 3 D3hot When the power state is changed from D3hot to D0 DS 1S resets the ...

Page 29: ...6 b5 b4 b3 b2 b1 b0 SPR7 SPR6 SPR5 SPR4 SPR3 SPR2 SPR1 SPR0 b0 SPR0 Secondary AC 97 Power Down Control 0 This bit controls the power state of the ADC and Input Mux in the Secondary AC 97 0 Normal default 1 Power down b1 SPR1 Secondary AC 97 Power Down Control 1 This bit controls the power state of the DAC in the Secondary AC 97 0 Normal default 1 Power down b2 SPR2 Secondary AC 97 Power Down Contr...

Page 30: ...e power control register in the Secondary AC 97 Respective data set to b 7 0 are correspondingly set into the Power down Control Status register in the Secondary AC 97 via the AC Link These are not set into the power down register in the Primary AC 97 60 61h FM Synthesizer Base Address Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FM Sy...

Page 31: ...ddress of the MPU401 If b5 I O bit of 40h register is set to 1 b 9 1 bits are decoded by ignoring b 15 10 bits 66 67h Joystick Base Address Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Joystick Base Address b 15 0 Joystick Base Address This register sets the base address of the Joystick If b5 I O bit of 40h register is set to 1 b 9 0 b...

Page 32: ...g logical IDs To control the device with the BIOS the logical device IDs must be defined in the PnP BIOS extended ROM space The logical IDs are determined by how it is configured IDs and configuration are as follows Functions used Block Logical Device ID FM MPU401 SB Pro Joystick YMH0100 O O O YMH0101 O The blocks pertain to the following FM Points to the FM synthesizer mapped to AdLibBase 0x0388 ...

Page 33: ...rotocol Yamaha recommends the combination of PC PCI and Serialized IRQ The system block diagram when using Intel chip set is shown below IRQ11 IRQ10 IRQ9 IRQ7 PCREQ IRQ5 PCGNT South Bridge PIIX4E PCI Control Address Data North Brigde 430TX 440BX SERIRQ Select either protocols DS 1S The PCI to ISA bridge needs to support PC PCI IRQ is directly connected to the IRQ input pins on the PCI to ISA bridg...

Page 34: ...The following shows the FMBase I O map of FM Synthesizer FMBase R Status Register port FMBase W Address port for Register Array 0 FMBase 1 R W Data port FMBase 2 W Address port for Register Array 1 FMBase 3 R W Data port The default FMBase value is 0x0388 The following shows the FM Synthesizer Block registers 2 1 1 Status Register FM Synthesizer Status Register RO Address D7 D6 D5 D4 D3 D2 D1 D0 x...

Page 35: ...HY BD SD TOM TC HH C0 C8h 6 6 CHR CHL FB CNT E0 F5h 5 WS FM Synthesizer Data Register Array 1 R W Address D7 D6 D5 D4 D3 D2 D1 D0 00 01h LSI TEST 04h CONNECTION SEL 05h NEW 20 35h 1 AM VIB EGT KSR MULT 40 55h 2 KSL TL 60 75h 3 AR DR 80 95h 4 SL RR A0 A8h F NUM L B0 B8h KON BLOCK F NUM H C0 C8h 6 6 CHR CHL FB CNT E0 F5h 5 WS 1 26h 27h 2Eh and 2Fh do not exist 2 46h 47h 4Eh and 4Fh do not exist 3 66...

Page 36: ...o SBBase R FM Synthesizer Status port SBBase W FM Synthesizer Address port for Register Array 0 SBBase 1h R W FM Synthesizer Data register SBBase 2h W FM Synthesizer Address port for Register Array 1 SBBase 3h R W FM Synthesizer Data port SBBase 4h W SB Mixer Address port SBBase 5h R W SB Mixer Data port SBBase 6h W SB DSP Reset port SBBase 8h R FM Synthesizer Status port SBBase 8h W FM Synthesize...

Page 37: ...cle DMA mode digitized sound output 75h o 8bit to 4bit ADPCM single cycle DMA mode digitized sound output with ref byte 76h 8bit to 3bit ADPCM single cycle DAM mode digitized sound output 77h 8bit to 3bit ADPCM single cycle DMA mode digitized sound output with ref byte 7Dh o 8bit to 4bit ADPCM auto init DMA mode digitized sound output with ref byte 7Fh 8bit to 3bit ADPCM auto init DMA mode digitiz...

Page 38: ...Suspend Resume F8h SBI IRQ Status The registers marked with exist but do not function DS 1S does not have the circuit that corresponds to the SB Mixer Therefore the volume settings on the SB Mixer are converted to the DSP coefficients of DS 1S or to AC 97 register values The conversion for each case is described below 1 SB Mixer DSP The volume of master MIDI and Voice are applied to this case When...

Page 39: ...ume for Voice Voice Vol 04h 0 1 2 3 4 5 6 7 mute mute mute mute mute mute mute mute 0 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h mute 56dB 46dB 40dB 36dB 34dB 32dB 30dB 1 0000h 0019h 0052h 00A3h 0103h 0146h 019Bh 0206h mute 46dB 36dB 30dB 26dB 24dB 22dB 20dB 2 0000h 0052h 0103h 0206h 0335h 0409h 0515h 0666Eh mute 40dB 30dB 24dB 20dB 18dB 16dB 14dB 3 0000h 00A3h 0206h 0409h 0666h 080Eh 0A24h 0...

Page 40: ...ster Power Down Request This bit stops the internal state of the Sound Blaster block 0 Normal default 1 Stop b1 SE Scan Enable This bit Shifts the internal state by 1 bit Setting a 1 followed by a 0 shifts the internal state b2 SM Scan Mode This bit sets whether to read or write the state 0 Write default 1 Read b3 SS Scan Select This bit gives permission to read or write the internal data to the S...

Page 41: ...zer F3h Current FM Synthesizer Array Read Only Default 00h b7 B6 b5 b4 b3 b2 b1 b0 CFA b0 CFA Current FM Synthesizer Arary This bit indicates that the FM Synthesizer array is being currently set to Array 0 or 1 0 Array 0 default 1 Array 1 F4h FM Synthesizer MPU401 Status Read Only Default 80h b7 b6 b5 b4 b3 b2 b1 b0 FFEMP FFFUL MPUS b0 MPUS MPU401 Status This bit indicates current MPU401 status 0 ...

Page 42: ...reading internal state shifting internal state scan data out 1 bit at a time 8 times N times internal state scan data out Scan Data Read Suspend Preparation ii Scan In SBPDA 0 SBPDR 1 SBPDA 1 SM 0 SS 1 not ready for scanning internal state data inhibit further DMA internal state shutdown ready for scanning internal state data internal state write in writing internal state shifting internal state s...

Page 43: ...de of MPU401 Full duplex operation is possible using the 16 byte FIFO for each direction transmitting and receiving The following shows the MPUBase I O map for MPU401 MPUBase R W MIDI Data port MPUBase 1h R Status Register port MPUBase 1h W Command Register port port D7 D6 D5 D4 D3 D2 D1 D0 0h Data 1h W Command 1h R DSR DRR 2 4 Joystick JSBase R W port D7 D6 D5 D4 D3 D2 D1 D0 0h JBB2 JBB1 JAB2 JAB...

Page 44: ...ro sound data on the PCI bus 3 1 PC PCI DS 1S provides two signals PCREQ and PCGNT to realize the PC PCI The format of the signals is shown below DS 1S asserts PCREQ and sets PCREQ to HIGH using the PCICLK corresponding to the DMA channel it is going to use In addition DS 1S determines whether the next PCI I O cycle is its own from the channel information that is encoded in PCGNT start CH0 CH1 CH2...

Page 45: ...6 23 Base 2h R Current Address 16 23 Base 3h W Base Address 24 31 Base 3h R Current Address 24 31 Base 4h W Base Word Count 0 7 Base 4h R Current Word Count 0 7 Base 5h W Base Word Count 8 15 Base 5h R Current Word Count 8 15 Base 6h W Base Word Count 16 23 Base 6h R Current Word Count 16 23 Base 7h N A Reserved Base 8h W Command Base 8h R Status Base 9h W Request Base Ah N A Reserved Base Bh W Mo...

Page 46: ...IRQ10 IRQ11 SERIRQ INTA INTA PCI Audio PCI Audio can only use INTA but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the three protocols The protocol can be switched using 40 43h Legacy Audio Control Register of the PCI Configuration Register 4 1 Serialized IRQ Serialized IRQ is a method to encode IRQs of 15 channels into one signal DS 1S provides the SERIRQ pin ...

Page 47: ...ow register remains in the same value and the other channel shadow register will only be decremented If both of channel shadow registers have been already set to minimum values they remain in the same values The master volume for the AC 97 is updated automatically via the AC Link by setting corresponding values to the shadow registers When both of the VOLUP and VOLDW pins are at LOW level at the s...

Page 48: ...put is selected from three types of data indicated below A Dolby digital AC 3 encoded data B Output data to be provided to the DAC slot on the AC link after digital mixing C Input data applied to the SPDIFIN pin When the above A and B data are supplied as outputs output sampling frequency is fixed at 48 kHz and when the above C data is supplied as an output output sampling frequency is dependent o...

Page 49: ... in the format defined below This is generally called I2 S format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LEFT Channel RIGHT Channel SCLK DATA LRCK In the Zoomed Video Port synchronization with a master clock supplied from the bus is inherently required However DS 1S can asynchronously process audio signal input via the Zoomed Video Port eliminating the need for...

Page 50: ...SYNC SDATA_OUT RESET SDATA_IN CBCLK CSYNC CSDO CSDI0 RST GPIO2 DOCKEN CSDI2 DVDD CODEC ID 01 Isolation Buffer When digital docking interface is made with the main side PC side powered on but docking station side powered off it may be not desirable for the secondary AC 97 that each output signal from the AC Link is applied to the secondary AC 97 that remains in powered off state In order to avoid s...

Page 51: ...D CVDD LVDD VDD3 0 3 4 6 V Input Voltage VIN 0 3 7 0 V Operating Ambient Temperature TOP 0 70 C Storage Temperature TSTG 50 125 C Note PVSS VSS 0 V 2 Recommended Operating Conditions Item Symbol Min Typ Max Unit Power Supply Voltage PVDD VDD CVDD LVDD VDD3 3 00 3 30 3 60 V Operating Ambient Temperature TOP 0 25 70 C Note PVSS VSS 0 V ...

Page 52: ... Voltage 3 VOL3 7 IOL3 6 0mA 0 1VDD3 V High Level Output Voltage 4 VOH4 8 IOH4 0 7mA 2 4 V Low Level Output Voltage 4 VOL4 8 IOL4 2 0mA 0 4 V High Level Output Voltage 5 VOH5 9 IOH5 4 0mA 2 4 V Low Level Output Voltage 5 VOL5 9 IOL5 12 0mA 0 4 V Input Pin Capacitance CIN 5 15 pF Clock Pin Capacitance CCLK 5 15 pF IDSEL Pin Capacitance CIDSEL 5 15 pF Output Leakage Current IOL 10 10 µA Normal TBD T...

Page 53: ... 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V t XI24 XICYC tXIHIGH 1 0 V 1 65 V 2 3 V tXILOW Fig 1 XI24 Master Clock timing 4 2 Reset Fig 2 Item Symbol Min Typ Max Unit Reset Active Time after Power Stable tRST 1 ms Power Stable to Reset Rising Edge tRSTOFF 10 ms Reset Slew Rate 50 mV ns Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V CL 50 pF RST PVDD LVDD VDD CVDD 3 0 V 0 8 V t...

Page 54: ...y tPOFF 28 ns tPSU Bused signal 7 ns 11 Point to Point 10 ns Input Setup Time to PCICLK tPSU PTP 12 Point to Point 12 ns Input Hold Time for PCICLK tPH 0 ns Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V CL 10 pF 11 This characteristic is applicable to REQ and PCREQ signal 12 This characteristic is applicable to GNT and PCGNT signal t PCICLK PCYC tPHIGH 0 3 VDD3 0 4 VDD...

Page 55: ...40 69 ns CMCLK High Time tCMHIGH 8 ns CMCLK Low Time tCMLOW 8 ns CMCLK Rising Time tCMR 4 6 ns CMCLK Falling Time tCMF 2 1 ns Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V CL 50 pF t CMCLK CMCYC tCMF tCMR tCMHIGH 0 2 VDD3 0 5 VDD3 0 8 VDD3 tCMLOW Fig 5 Master Clock timing for AC 97 ...

Page 56: ... ns Output Hold Time for CBCLK tCOH 13 0 ns Input Setup Time to CBCLK tCISU 14 15 ns Input Hold Time for CBCLK tCIH 14 5 ns Warm Reset Width 1 3 µs Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V CL 50 pF 13 This characteristic is applicable to CSYNC and CSDO signal 14 This characteristic is applicable to CSDI signal CBCLK SYNC CSDI CSDO 0 8 V 1 5 V 2 0 V 0 8 V 2 0 V 0 8...

Page 57: ... ZVLRCK Setup Time tSLRS 32 ns ZVBCLK Low Time tSCLKL 22 ns ZVBCLK High Time tSCLKH 22 ns ZVSDI Setup Time tSDS 32 ns ZVSDI Hold Time tSDH 2 ns Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V CL 50 pF tSDH tSDS tSCLKH tSCLKL tSLRS tSLRD ZVLRCK ZVSCLK ZVSDI Fig 7 Zoomed Video Port timing ...

Page 58: ...0 0 40 1 00 0 15 0 50 0 30 1 40 0 20 The shape of the molded corner may slightly different from the shape in this diagram The figure in the parenthesis should be used as a reference Plastic body dimensions do not include burr of resin UNIT mm Note The LSIs for surface mount need especial consideration on storage and soldering conditions For detailed information please contact your nearest agent of...

Page 59: ...KNESS 0 125Typ or 0 15Typ The shape of the molded corner may slightly different from the shape in this diagram The figure in the parenthesis should be used as a reference Plastic body dimensions do not include burr of resin UNIT mm Note The LSIs for surface mount need especial consideration on storage and soldering conditions For detailed information please contact your nearest agent of Yamaha ...

Page 60: ... OF NON INFRINGEMENT WITH RESPECT TO THE PRODUCTS YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS INFRINGEMENT OF ANY THIRD PARTY S INTELLECTUAL PROPERTY RIGHTS INCLUDING THE PATENT COPYRIGHT TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY 5 EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERF...

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