Yamaha HTR-6290, Service Manual

Page: 83 / 198

RX-V1900/HTR-6290/DSP-AX1900
83
No. Function Name TYPE
(1)
PULL
(2)
GPIO
(3)
Detail of Function
64 EM_D[9] IO – N EMIF data bus [lower 16-Bits]
65 Core Supply (CVpp)
66 EM_D[8] IO – N EMIF data bus [lower 16-bits]
67 EM_WE_DQM[1] O – N Write enable or byte enable for EM_D [15:8]
68 IO Supply (DVpp)
69 Ground(Vss)
70 EM_CLK O – N SDRAM clock
71 EM_CKE O – N SDRAM clock enable
72 Ground(Vss)
73 IO Supply (DVpp)
74 EM_A[11] O – N EMIF address bus
75 EM_A[9] O – N EMIF address bus
76 EM_A[8] O – N EMIF address bus
77 Core Supply (CVpp)
78 Ground(Vss)
79 EM_A[7] O – N EMIF address bus
80 EM_A[6] O – N EMIF address bus
81 IO Supply (DVpp)
82 Ground(Vss)
83 EM_A[5] O – N EMIF address bus
84 EM_A[4] O – N EMIF address bus
85 Core Supply (CVpp)
86 EM_A[3] O – N EMIF address bus
87 Ground(Vss)
88 EM_A[2] O – N EMIF address bus
89 EM_A[1] O – N EMIF address bus
90 Core Supply (CVpp)
91 EM_A[0] O – N EMIF address bus
92 IO Supply (DVpp)
93 EM_A[10] O – N EMIF address bus
94 EM_BA[1] O – N
SDRAM bank address and asynchronous memory Low-Order
address
95 Ground(Vss)
96 EM_BA[0] O – N
SDRAM bank address and asynchronous memory Low-Order
address
97 EM_CS[0] O – N SDRAM chip select
98 EM_RAS O – N SDRAM row address strobe
99 Ground(Vss)
100 EM_CS[2] O – N Asynchronous memory chip Select
101 Core Supply (CVpp)
102 EM_RW O – N Asynchronous memory read/not write
103 IO Supply (DVpp)
104 EM_OE O – N SDRAM output enable
105 SPI0_ENA/I2C1_SDA IO – Y SPI0 enable (ready) or I2c1 serial data
106 Ground(Vss)
107 SPI0_ENA/I2C1_SCL IO – Y SPI0 enable (ready) or I2c1 serial clock
108 SPI0_CLK/I2C0_SCL IO – Y SPI0 serial clock or I2c0 serial clock
109 Ground(Vss)
110 SPI0_SIMO IO – Y SPI0 data pin slave in master out
111 SPI0_SOMI/I2C0_SDA IO – Y SPI0 data pin slave out master in or I2C0 serial data
112 IO Supply (DVpp)
113 AXR0[0] IO – Y McASP0 serial data 0
114 Ground(Vss)
115 AXR0[1] IO – Y McASP0 serial data 1
116 AXR0[2] IO – Y McASP0 serial data 2
117 AXR0[3] IO – Y McASP0 serial data 3
118 Ground(Vss)
119 AXR0[4] IO – Y McASP0 serial data 4
120 AXR0[5]/SPI1_SCS IO – Y McASP0 serial data 5 or SPI1 slave chip select
121 AXR0[6]/SPI1_ENA IO – Y McASP0 serial data 6 or SPI1 enable (ready)
122 AXR0[7]/SPI1_CLK IO – Y McASP0 serial data 7 or SPI1 serial clock
123 Core Supply (CVpp)
124 Ground(Vss)
No. Function Name TYPE
(1)
PULL
(2)
GPIO
(3)
Detail of Function
125 IO Supply (DVpp)
126 AXR0[8]/AXR1[5]/SPI1_SOMI IO – Y
McASP0 serial data 8 or McASP1 serial data 5 or SPI1 data pin slave
out master in
127 AXR0[9]/AXR1[4]/SPI1_SIMO IO – Y
McASP0 serial data 9 or McASP1 serial data 4 or SPI1 data pin slave
in master out
128 Core Supply (CVpp)
129 Ground(Vss) IO – Y
130 AXR0[10]/AXR1[3] IO – Y McASP0 serial data 10 or McASP1 serial data 3
131 AXR0[11]/AXR1[2] McASP0 serial data 11 or McASP1 serial data 2
132 Core Supply (CVpp)
133 Ground(Vss) IO – Y
134 AXR0[12]/AXR1[1] IO – Y McASP0 serial data 12 or McASP1 serial data 1
135 AXR0[13]/AXR1[0] McASP0 serial data 13 or McASP1 serial data 0
136 IO Supply (DVpp) IO – Y
137 AXR0[14]/AXR2[1] IO – Y McASP0 serial data 14 or McASP2 serial data 1
138 AXR0[15]/AXR2[0] IO – Y McASP0 serial data 15 or McASP2 serial data 0
139 ACLKR0 McASP0 receive bit clock
140 Ground(Vss) IO – Y
141 AFSR0 IO – Y McASP0 receive frame Sync (L/R clock)
142 ACLKX0 IO – Y McASP0 transmit bit clock
143 AHCLKR0/AHCLKR1 IO – Y McASP0 and McASP1 receive master clock
144 AFSX0 McASP0 transmit frame Sync (L/R clock)