Yamaha HTR-6280, Service Manual

Page: 123 / 166

A
1 2 3 4 5 6 7 8 9
10
BCD
E
F
G
H
I
J
K
L
MN
123
DIGITAL 5/5
RX-V1065/HTR-6280/AX-V1065
●
電圧は、内部抵抗
10MΩの電圧計で測定したものです。
●
⚠印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、 パーツリストに記載されている部品を使用してください。
●
本回路図は標準回路図です。改良のため予告なく変更することがございます。
★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
IC73
IC74
CB73
CB72
CB71
CB70
IC75
IC75
IC76 IC77 IC78
IC71
IC70
IC72
0.6
1.8
1.8
1.7
1.8
1.5
3.3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.4
1.2
1.1
1.0
1.4
0
0
0
0
0
0
0
2.1
3.4
0.9
3.4
1.8
1.8
1.8
3.4
3.4
3.3
3.4
1.0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.4 2.1
3.4
3.4
0.7
0.8
0.8
1.0
0.8
0
0
0
1.7
3.4
3.4
3.4
3.4
3.4
1.8
1.8
1.6
0
0
0
0
0
0
0
0
0
0
1.6
1.6
1.7
1.7
0
2.5
2.5
1.7
1.7
3.4
3.4
1.5
0
1.8
0
0
0
0
0
0
0
0
1.8
1.8
1.8
1.9
1.8
2.6
1.9
3.4
3.4
3.4
3.4
3.1
0.4
0
0
0
0
0
0
0
5.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.9
0
0
1.9
1.8
1.8
1.8
1.8
1.8 1.8
1.9
1.8
1.9
3.4
3.4
5.6
0
3.4
0
3.4
1.8
0
1.8
0
3.4
1.9
1.8
3.2
3.2 3.4 3.4
3.4 3.4 3.4 2.6 2.6 3.4 0.9 1.9 2.0
1.6
0 0 0 0 0
1.2
0 0 0
0 0 0
0 0 0 0 0 0 0
0 0
0.7 0.3 0.4 1.7
0
0.6 0.9 0.9
0
0
0 0
1.7 1.6 1.7
0 0 0 0 0 0
1.3
0
0.7
2.5 2.5
1.5 1.3
0 0
3.3 3.3 3.2
2.5 2.5 3.3
0
1.7 0 0 0
0 0 0 1.9 1.9 1.9
2.6 0.2 0.4
0
0
0 0 0 1.7 1.7 1.6 1.5 1.8 0 1.7 0 1.5
0
1.9
3.4
3.4
0
1.8
1.8
2.7
1.7
0 0 0 0
1.5 1.9 1.8 1.8 3.4 2.6
0
1.7 3.4 3.4 1.3 1.7 1.6 1.7
0 0 0 0 0
1.7 1.7 1.6 1.6 1.6
3.2 3.3
0
0
0
0
0
3.3
3.4
3.4
1.7
1.3
2.5 3.4 3.4 2.5
1.3
3.2 3.3
0 0 0 0 0
1.0
0
0.9 1.1 1.2 1.4
0 0 0 0
3.4 1.4
3.4 1.7 1.8
1.7
1.8 0 1.8
3.3 3.3
1.7 1.7
1.6
2.7
0 0 0.7 0.8 0.8 1.0 0 0 0 0 0.8 0 0 1.7
3.3 3.2 3.2 0.9
1.6 1.6 1.6 1.6
3.3
0
0.6
0 0
1.9
POINT
E XL70 (Pin 81 of IC70)
E
IC71
: ABT1012Q100
Advanced video processor device
CUE/
Shar
pness/
Y
C
Dela
y
Bor
der Gen.
Masking Gen.
P
anor
ama
P
rocessor
Int
erf
ace &
Co
n
tro
l
R
egist
er
s
10
HD Scaler
S
ync Gener
at
or
T
ri-S
ync
Gener
at
or
T
est P
a
tt
er
n
Gener
at
or
D
ynamic
R
ange
Expansion
C
olor Space
C
o
n
v
er
sion
D
ynamic R
a
nge
C
ompr
ession
Scaler Bypass
Video Input
1
2-bits in
Y
;
1
2-bits in C
1
0-bits in
Y
;
1
0-bits in C
Video T
iming
Gener
at
or
Cloc
k Gener
ation
27MHz
ABT1
0
1
2
27MHz
(optional) Video output cloc
k
1
50MHz
Video Out Clk
10
12
12
12
10
12 12
12
10
10
10
Pin t
o
Pin Bypass
I2C
20
Input Video
Output Video
24
Input F
o
rmat/
C
olor Space
Decoder
Output F
o
rmat
Co
nve
rt
e
r
Pictur
e C
o
ntr
ols
3x3 Input matr
ix
Input
Bus
Mapping
Output
Bus
Mapping
12
3x3 Output
Matr
ix
12
12
INPUT MUX
OUTPUT FIFO AND FORMATTER
IC70
: AD
V7800BS
TZ-80
1
0-bit, SDTV/HDTV 3D comb f
ilt
er
, video decoder and g
raphics digitiz
er
CLAMP
12
ANTIALIAS
FILTER
ADC
24
P30 TO P53
GRAPHICS RGB
AIN1
AIN12 CVBS
S-VIDEO
SCART-
(CBVS+RGB)
YPrPb
TO
CVBS OUT
FB
HS_IN2 VS_IN2
HS_IN VS_IN
SOG SOY
SCLK
SCLK2
SDA
SDA2 ALSB
INT
CLK_IN
DE_IN
10
CLAMP
ANTIALIAS
FILTER
ADC
10
CLAMP
ANTIALIAS
FILTER
ADC
10
2D COMB
CLAMP
DIGITAL INPUT PORT
DVI OR HDMI
SYNC PROCESSING AND
CLOCK GENERATION
SERIAL INTERFACE
CONTROL AND VBI DATA
COLORSPACE CONVERSION
SSPD
STDI
ANTIALIAS
FILTER
ADC
10
10 10 10 10
DAC
CORE
CLK
COMPONENT PROCESSOR (CP)
STANDARD DEFINITION PROCESSOR (SDP)
DDR/SDR-SDRAM INTERFACE DDR/SDR-SDRAM INTERFACE
VBI DATA PROCESSOR (VDP)
GAIN
CONTROL
MACROVISION
DETECTION
ACTIVE PEAK
AND AGC
DIGITAL
FINE
CLAMP
AV CODE
INSERTION
OFFSET
CONTROL
LLC SFL/SYNC_OUT FIELD/DE VS CS/HS PIXEL DATA P0 TO P53
AV CODE
INSERTION FAST BLANK
OVETLAY CONTROL
VERTICAL
PEAKING
MACROVISION
DETECTION
HORIZONTAL
PEAKING
CTI LTI
ITOP
STANDARD
AUTODECTION
COLORSPACE CONVERSION
525p/625p SUPPORT
3D COMB
TBC
MUX
54
IC73
: R1
1
72H1
81B-T1
-F
V
olt
age r
egulat
or
V
DD CE
Pin No
.
1 2 3 4 5
S
ymbol
CE
GND
NC V
DD
V
OUT
Descr
iption
Chip Enab
le Pin
Gr
ound Pin
No C
onnection
Input Pin Output Pin of
V
olt
age R
egulat
or
Vr
ef
45 12
Curr
ent Limit
V
OUT
GND
V
DD CE
Pin No
.
1 2 3 4 5
S
ymbol
CE
GND
NC V
DD
V
OUT
Descr
iption
Chip Enab
le Pin
Gr
ound Pin
No C
onnection
Input Pin Output Pin of
V
olt
age R
egulat
or
Vr
ef
45 12
Curr
ent Limit
V
OUT
GND
IC7
4
: R1
1
72H331D-T1
-F
V
olt
age r
egulat
or
1
DIR
A1 A2 A3 A4 A5 A6 A7 A8
GND
Vcc OE B1 B2 B3 B4 B5 B6 B7 B8
2 3 4 5 6 7 8 9
10
20 19 18 17 16 15 14 13 12 11
IC76-78
: SN74LVTH245APW
3.3 V ABT octal bus transceivers with 3-state outputs
IC75
:
TC7WZ32FK (TE85L, F)
D
ual 2-input OR g
a
te
1
1A
2
1B
3
2Y
4
GND
8
Vcc
71
Y
62
B
52
A
IC72
: AD
V71
72KS
TZ
Digit
al P
AL/NTSC video encoder
8 8
R
SET1
COMP1
AD
V71
72/AD
V71
73
COL
OR
D
ATA
P0
V
REF
R
SET2
COMP2
P7
D
A
C E
D
A
C F
D
A
C D
D
A
C A
D
A
C B
D
A
C C
BRIGHTNESS AND
CONTRA
S
T
CONTR
OL
+
ADD S
YNC
+
INTERPOLA
T
O
R
10
LUMA
PR
OGRAMMABLE
FIL
TER +
SHARPNESS
FIL
TER
S
A
TURA
TION CONTR
OL
+
ADD B
U
R
S
T
+
INTERPOLA
T
O
R
10
PR
OGRAMMABLE
CHR
OMA
FIL
TER
10
8 8 8
REAL
-TIME
CONTR
OL CIRCUI
T
SCRESET/R
TC
MODULA
T
O
R
+
HUE
CONTR
OL
10 10 10
10 10 10
Y
U
V
8
4:2:2 T
O
4:4:4
INTER-
POLA
T
O
R
10
10
SIN/COS
DDS BL
OCK
DA
C
CONTR
OL
BL
OCK
DA
C
CONTR
OL
BL
OCK
10 10 10
10 10
1
0-bit
DA
C
1
0-bit
DA
C
1
0-bit
DA
C
1
0-bit
DA
C
1
0-bit
DA
C
1
0-bit
DA
C
10
M U L T
I
P L E X E R M U L T
I
P L E X E R
YUV T
O
RBG
MA
TRIX
+
YUV
LEVEL
CONTR
OL
BL
OCK
I2
C MPU POR
T
HS
YNC
FIELD/
VS
YNC
BLANK
TTX
TTXREQ
V
AA
RESET
TELETEXT
INSER
TION BL
OCK Y
CrCb TO
YUV
MA
TRIX
CL
OCK
CSO_HSO
VSO
CLAMP
SCL
OCK
SD
A
T
A
AL
SB
VIDEO TIMING
GENERA
T
O
R
GND
P
AL_NTSC
VIDEO DECODER & I/P
SCALER
to
DIGI
T
AL 1/5
to
DIGI
T
AL 2/5
to VIDEO (9)_CB391
(B, G, E, F models
)
P
age 130
C3
to VIDEO (1)_CB304
P
age 128
J9