RX-V800/RX-V800RDS/HTR-5280
14
• The signal is output in digital full bit without including the head margin.
• The same applies as “DSP 0dB” except that the digital data is output in full bit
at D/A.
• However, the SWFR signal is not output in full bit.
DSP 0dB
[Remote control code: 7A-91 (PRG 10)]
• C/SWFR, FL/FR, RL/RR signals are output through DSP (see the signal path
in the figure below) without using the external DRAM. (Head margin included)
Head margin:
Main L/R: 0dBFS, Center: -6dBFS, Rear Center: -3dBFS, FL/FR: -6dBFS, RL/
RR: -12dBFS, SWFR: Add L/R signal at -20dBFS.
RR
CODEC
(A/D)
AK4527
ANALOG
AC3D3 YSS928
L/R
L/R
SDOA0
DIGITAL
INTERNAL
DIR
4M DRAM
D/A
AK4393
Main DSP
(Decoder)
Sub DSP
L
R
C/LFE
C/LFE
LS/RS
SDOB1
CODEC
(D/A)
AK4527
C
SWFR
LS/RS
SDOB2
FL
FR
SDOB3
RL
L/R
L/R
RR
CODEC
(A/D)
AK4527
ANALOG
AC3D3 YSS928
L/R
L/R
SDOA0
DIGITAL
INTERNAL
DIR
4M DRAM
D/A
AK4393
Main DSP
(Decoder)
Sub DSP
L
R
L/R
SDOB1
CODEC
(D/A)
AK4527
C
SWFR
L/R
L/R
SDOB2
FL
FR
SDOB3
RL
L/R
[2ch source]
[Multi ch source]
SDOxx represents a terminal name of AC3D3.
The shaded square ( ) means that the element indicated in it does not
operate.
DSP FULL BIT
[Remote control code: 7A-92 (PRG 11)]
Summary of Contents for HTR-5280 - AV Receiver - 5.1 Channel
Page 75: ...RX V800 RX V800RDS HTR 5280 ...
