Yamaha DVD-S2700, Service Manual

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DVD-S2700
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FCUIF[16]
MEMDA[8]
FCUIF[21]
MEMAD[5]
FCUIF[15]
VDDP
MEMDA[0]
FCUIF[2]
MEMAD[4]
FCUIF[14]
MEMRD#
FCUIF[1]
MEMAD[3, 2]
FCUIF[13, 12]
MEMCS[0]#
MEMAD[1]
FCUIF[11]
BOOTSEL[2]
MEMAD[0]
FCUIF[10]
BOOTSEL[1]
GNDP
VDD-IP
VDDP
RAMADD
[4, 3, 5, 2, 6]
VDDP
RAMADD
[1, 7, 0]
GNDP
RAMADD[8]
VDDC
RAMADD[10]
GNDC
RAMADD[9]
VDDP
RAMADD[11]
RAMCS[0]#
RAMBA[1]
RAMBA[0]
GNDP
RAMCS[1]#
RAMRAS#
RAMCAS#
VDDP
RAMWE#
RAMDQM
GNDPCLK
PCLK
VDDPCLK
RAMDAT[8]
GNDP
RAMDAT
[7, 9, 6]
VDDP
RAMDAT
[10, 5, 11]
GNDP
O
I/O
I/O
O
O
S
I/O
O
I/O
O
O
I/O
O
O
O
O
O
I
O
O
I
S
S
S
O
S
O
S
O
S
O
S
O
S
O
O
O
O
S
O
O
O
S
O
O
S
O
S
I/O
S
I/O
S
I/O
S
Flash card interface unit output signal
PNVM/SRAM bi-directional data bus
Flash card interface unit I/O signal
PNVM/SRAM address bus outputs
Flash card interface unit output signal
3.3 V digital periphery power supply
PNVM/SRAM bi-directional data bus
Flash card interface unit output signal
PNVM/SRAM address bus outputs
Flash card interface unit output signal
PNVM/SRAM read enable (active low) output
Flash card interface unit I/O signal
PNVM/SRAM address bus outputs
Flash card interface unit output signal
PNVM/SRAM chip select (active low) output
PNVM/SRAM address bus outputs
Flash card interface unit output signals
Microprocessor SW boot (and execute) source selection:
(high, high) - For production testing;
(high, low) - Flash+SRAM (for debug monitor);
(low, high) - First debug UART
(low, low) - Flash (low) or Level sampled during RESET
PNVM/SRAM address bus outputs
Flash card interface unit output signals
Microprocessor SW boot (and execute) source selection:
(high, high) - For production testing;
(high, low) - Flash+SRAM (for debug monitor);
(low, high) - First debug UART
(low, low) - Flash (low) or Level sampled during RESET
Digital periphery ground of 3.3 V supply
3.3 V periphery reference voltage
3.3 V digital periphery power supply
SDRAM address bus output
3.3 V digital periphery power supply
SDRAM address bus output
Digital periphery ground of 3.3 V supply
SDRAM address bus output
1.8 V digital core power supply
SDRAM address bus output
Digital core ground of 1.8 V supply
SDRAM address bus output
3.3 V digital periphery power supply
SDRAM address bus output
SDRAM chip select (active low)
SDRAM bank select output
SDRAM bank select output
Digital periphery ground of 3.3 V supply
SDRAM chip select (active low) output
SDRAM row select (active low) output
SDRAM column select (active low) output
3.3 V digital periphery power supply
SDRAM write enable (active low) output
SDRAM data masking (active high) output
Digital ground of filtered 3.3 V supply for PCLK
SDRAM clock output (same as internal processing clock)
3.3 V filtered digital power supply for PCLK
SDRAM bi-directional data bus
Digital periphery ground of 3.3 V supply
SDRAM bi-directional data bus
3.3 V digital periphery power supply
SDRAM bi-directional data bus
Digital periphery ground of 3.3 V supply
Pin Functions Direction Description
No.