Yamaha DSP-AX1900, Service Manual

Page: 78 / 198

RX-V1900/HTR-6290/DSP-AX1900
78
RX-V1
90
0/HTR-6290/
DSP-AX1
90
0
No. Port Name
Function Name
(P.C.B.)
I/O Detail of Function
1 TXDSIR TXDH SO Data transmission to VIDEO_CPU
2 SCKN CLKH SO Clock transmission to VIDEO_CPU
3 PRI LIMIT DA Limiter control output
4 LIMIT HDMINT TMR HDMI MUTE input
5 SDACEC TXDi SO iPod asynchronous serial data input
6 SDLCEC RXDi SI iPod asynchronous serial data output
7 /VSYNC /VSYNC TMR Vertical sync pulse INT
8 RSELDT0 RSELDT0 O Rec out SW1 control (ROHM) data (U, C, R, T, A, B, G, E, L models)
9 RSELCK0 RSELCK0 O Rec out SW1 control (ROHM) clock (U, C, R, T, A, B, G, E, L models)
10 ISELDT0 ISELDT0 O Rec out SW1 control (ROHM) data
11 ISELCK0 ISELCK0 O Rec out SW1 control (ROHM) clock
12 HDIMT /CSDAC2 O Tl#1 initial clear
13 /CSDAC1 /CSDAC1 O 2sh DAC (PCM1791A) *6 chip enable
14 CEC_D /CSY O TI#1 chip enable
15 BYTE BYTE MCU External data bus width change: 16bit
16 CNVSS CNVSS MCU Processor mode select: Single chip mode
17 /ICD /ICD O DIR initial clear
18 /ICTI /ICTI I TI#1 SPI READY
19 /RES /RES MCU
20 XOUT XOUT MCU
21 VSS VSS MCU
22 XIN XIN MCU
23 VCC VCC MCU
24 NMI NMI IRQ
25 REM2 REM1 IRQ Remote control pulse input 1
26 PDET PDET IRQ Power detect
27 RXDR RXDR IRQ RS232C · YDC signal reception detect
28 iPDET iPDET TMR iPod detect
29 PLLR/RXDHDR /CSTI O TI#0 (IC534 DSP P.C.B.) chip enable
30 TUCK /ICXM O DABIC IC reset (U model)
(RDSCE) O RDS enable (G model)
31 TUDA/TXDHDR XMPWR O XM Radio power control (U, C models)
32 /ITNTTI /ITNTI TMR TI#0/#1 (DA70Y) interrupt
33 /INTCEC /CSSIR O DIR chip enable
34 /INTDIR /INTDIR TMR DIR interrupt
35 SPIRDY /SPIRDY I TI DA70Y serial ready / DIR WCK input (WCK input for CDDA writing)
36 DRXM DRXM SI DABIC IC RxD (XM data reception) (U, C models)
37 DTXM DTXM SO DABIC IC TxD (U, C models)
38 TXDH TXDR SO
Usually RS-232C asynchronous communication data output / Data transmis-
sion terminal for AF220
39 VCC VCC MCU
40 RXDH RXDR SI
Usually RS-232C asynchronous communication data input / Data reception
terminal for AF220
41 VSS VSS MCU
42 RTSH RTS SO Usually RS-232C asynchronous RTS output
43 CTSH CTS I Usually RS-232C asynchronous CTS input
44 TXDD (SDM) TXDD (SDM) SO Serial data output to DIR, TI, DAC
45 RXDD (SDD) RXDD (SDD) SI Serial data reception to DIR, TI, DAC
46 CLKD (SCK) CLKD (SCK) SO Serial clock output to DIR, TI, DAC
47 DMT DMT O Digital full mute (Hi=Mute)
48 DIRSDO DIRSDO I Usable for both CDDA write data input/XM LINK ACTIVE
49 /CSTI TUDA O PLL data output for tuner
50 /SCY TUCK O PLL clock output for tuner
51 XMPWR PLLR I PLL reception for tuner
52 /TMUTE /TMUTE O TUNER mute output
53 TUNED TUNED I TUNER TUNED input
54 TUCE/HDR_PE TUCE O PLL chip select for TUNER
55 /ST /ST I TUNER STEREO detect input
56 CKZEV CKZEV O
ZONE tone control IC serial transmission clock (U, C, R, T, K, A, B, G, E, L
models)
57 VSS VSS MCU