Yamaha DSP-AX1, Service Manual

Page: 59 / 103

A
BCD
E
F
G
H
1 2 3 4 5 6
IJ
K
L
M
N
O
7 8 9
10
DSP-AX1/RX-V1
L/R
L/R
LS/RS
RC
C/LFE
C/RC
CENTER
L/R
C/LFE
FL/FR
FL/FR
FR
ONT L
RC
RC
RL/RR
L
FL/FR
FL/FR
RL/RR
RL/RR
L/R
L/R
C/RC C/LFE
REAR CENTER
RL/RR
REAR L
0
0
0
0.2
4.8
4.8 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 4.8
3.2
2.0 2.5 4.6 1.6
4.8
4.8
4.8
4.8
4.8
4.4
4.8 4.8
4.8
4.8
4.8
4.8
2.4
2.4
2.5
0
~
~
0
0
4.8
4.8
2.3
2.4
~
0
0
0
0
0
4.8 4.8
4.8
4.8
4.8
4.8
2.4
2.4
2.5
0
~
~
0
0
4.8
4.8
2.3
2.4
~
0
0
0
0
0
4.8
4.8
4.8
4.8
4.8
4.8
2.4
2.4
2.5
0
~
~
0
0
4.8
4.8
2.3
2.4
4.4
0
0
0
0
0
4.8 4.8
4.8
4.8
4.8
4.8
2.4
2.4
2.5
0
~
~
0
0
4.8
4.8
2.3
2.4
4.4
0
0
0
0
0
4.8 4.8
4.8
4.8
4.8
4.8
2.4
2.4 2.4
4.9
-4.8
2.6
-4.8
-4.8
-2.3
0
0
2.6
4.9
0
0
0
0
0
0
11.5 11.5
0
-2.2
~
0
2.6
0
~
~
0
0
4.8
4.8
2.3
2.4
3.0
0
0
0
0
0
0 0
0
0
~
~
4.8
3.2
0
2.4
4.8
4.7
4.7
4.8
2.5
2.5
0
0
2.3
4.7
4.8
4.8
4.8
4.8
4.8
4.8
4.8
3.2
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
0
0
0
~ ~ ~ ~ ~ ~ ~ ~ ~ 0 0
0
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.1
0.1
4.8
3.2
0
0
0
0
0
3.2
4.8
0 0 0 0 0
0
0 0 0
4.8
4.8
3.2
4.8
~
~
~ ~ ~ ~ ~ ~
~ ~
~ ~
0.1
0.1
0.1
0.2
0.2
0.2
0.2
0.2
0.2
4.8
4.8
4.6
2.0
0.2
0.2
0.2
0.2
2.5
2.5
1.6
~
~
~
~
~
4.8
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
4.8
4.8
0
0
1.6
1.6
1.6
1.6
1.6
1.6
3.9
3.9
4.1
~
~
~
~
~
0 4.8
2.4
2.4
2.4
2.4
3.6
4.3
1.6
1.6
1.6
1.6
1.5
4.8
3.2
4.8 1.5 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 3.5 1.6 4.8
0
2.4 2.4 2.4 2.4 ~ ~ ~ ~ ~ 0 3.2
3.6 3.9 4.3 4.1 4.8
3.2
4.8
4.7
4.7
4.8
4.8
4.8
4.8
4.8
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
0
0
3.2
4.8
0
2.5
2.3
0
0
0
0
1.6 1.6 0 1.7
0
4.8
3.2
0
0
3.2
4.8 0
3.0
4.4 4.4 1.8 4.4
4.8
0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 0 0 0 0 0
4.8
4.8
3.2
0
0
1.6
4.8
1.7
1.6
3.5
4.6
2.0
~
~
~
~
~
~
~
~
0.2
0.2
0.2
0
0
0
0.2
0.2
0.2
0.2
0.2
2.5
2.5
1.6
~
~
~
~
~
0.2
0.2
0.2
t
2.4
4.9
-4.8
2.5
-4.8
-2.3
0
0
2.7
4.9
0
0
0
0
0
0
11.5 11.5
0
-2.1
~
0
2.4
4.9
-4.8
2.5
-4.8
-2.3
0
0
2.6
4.9
0 0
0
0
0
0
11.5 11.5
0
-2.1
~
0
2.4
4.9
-4.8
2.5
-4.8
-2.3
0
0
2.6
4.9
0 0
0
0
0
0
11.5 11.5
0
-2.2
~
0
2.4
4.9
-4.8
2.5
-4.8
-2.3
0
0
2.6
4.9
0 0
0
0
0
0
11.5 11.5
0
-2.2
~
0
2.4
4.9
-4.8
2.6
-2.3
0
0
2.7
4.9
0 0
0
0
0
0
-11.5
-11.5
0
-2.2
~
0
-4.8
2.4
4.9
-4.8
2.5
-2.3
0
0
2.6
4.9
0
0
0
0
0
0
-11.5 -11.5
0
-2.2
~
0
-4.8
2.4
4.9
-4.8
2.5
-2.3
0
0
2.6
4.9
0 0
0
0
0
0
-11.5
-11.5
0
-2.2
~
0
-4.8
2.4
4.9
-4.8
2.5
-2.3
0
0
2.6
4.9
0 0
0
0
0
0
-11.5
-11.5
0
-2.2
~
0
-4.8
2.4
4.9
-4.8
2.5
-2.3
0
0
2.6
4.9
0
0
0
0
0
0
-11.5
-11.5
0
-2.2
~
0
DSP6
DSP6
DIGITAL FILTER
DAC
RAM
RAM
RAM
■
SCHEMA
TIC
DIAGRAM
(DSP(1)-2)
*
All voltage are measured with a 10M
Ω
/V DC electric volt meter.
*
Components having special characteristics are marked
Z
and
must be replaced with parts having specifications equal to those originally installed.
*
Schematic diagram is subject to change without notice.
Point
t
(Pin 3 of IC7)
V : 1V/div, H : 50 nsec/div DC, 1 : 1 probe
0V
IC10, 11, 13, 14, 16, 17, 19, 20, 22, 23 : PCM1704F 24 bit D/A Converter
IC47~56 :
µ PC4570G2
Dual OP-Amp
–
+
OUT
1
–IN
1
–V
CC
+V
CC
OUT
2
1 2 3 4
5
+IN
1
–IN
2
+IN
2
–+
6 7 8
IC33 ~ 35 : MSM514260C-60JS 262,144-word x 16 bit Dynamic RAM
1
VCC
2
DQ1
3
DQ2
4
DQ3
5
DQ4
6
VCC
7
DQ5
8
DQ6
9
DQ7
10
DQ8
11
NC
12
NC
13
WE
14
RAS
15
NC
16
A0
17
A1
18
A2
19
A3
20
VCC
40
VSS
39
DQ16
38
DQ15
37
DQ14
36
DQ13
35
VSS
34
DQ12
33
DQ1
1
32
DQ10
31
DQ9
30
NC
29
LCAS
28
UCAS
27
OE
26
A8
25
A7
24
A6
23
A5
22
A4
21
VSS
TIMING
GENERA
T
O
R
I/O
CONTROLLER
I/O
CONTROLLER
COLUMN
DECODERS
SENSE
AMPLIFIERS
I/O
SELECT
OR
OUTPUT
BUFFERS
OUTPUT
BUFFERS
INPUT
BUFFERS
INPUT
BUFFERS
MEMOR
Y
CELLS
COLUMN
ADDRESS
BUFFERS
INTERNAL ADDRESS COUNTER
REFRESH
CONTROL
CLOCK
ROW
DECODERS
WORD
DRIVERS
ON CHIP
VBB GENERA
T
O
R
ROW
ADDRESS
BUFFERS
RAS
LCAS
UCAS A0~A8
VCC VSS
WE
OE
DQ1~DQ8 DQ9~DQ16
99
16
16
8 8
8 8
8 8
8 8
99
REF DC
SERVO DC
—VDD
DGND
+VDD
—VCC
AGND
+VCC
BPO DC
19
17
4
5
6
20
16
11
12
14
SERIAL
INPUT
I/F
&
CONTROL
LOGIC
23—BIT
DAC
A
23—BIT
DAC B
BIPOLAR OFFSET
REFERENCE
&
SER
VO
POWER SUPPL
Y
10
9 1 7 2
3 8
13 18
IOUT NC NC NC NC
BCLK WCLK
D
ATA
20BIT
INVER
T
IC9, 12, 15, 18, 21 : DF1704E 24 bit Digital Filter
SERIAL INPUT
I/F
8X OVERSAMPLING
DIGIT
AL
FIL
TER
WITH
FUNCTION CONTROLLER
OUTPUT
I/F
MODE
CONTROL
I/F
CR
YST
AL
OSC
POWER SUPPL
Y
2
28
1
11 12 13 10 15 14 16
17
18
27
6
4
3
5
26 25 24 23
19
20
7
9
22
8
BCKIN LRCIN
DIN
BCKO WCKO DOL DOR
SF0
SF1
SRO
IIS
IW0
IW1
OW0
OW1
XTI
XTO
CLKO
VDD
VSS
MD/CKO MC/LRIP
ML/RESV
MODE
MUTE
RST
DEM
SCK
IC57 : HD74HC00FPEL Quad 2 Input NAND A1 B1 A2
V
DD
B4
1 2 3 4
11
Y1
A4 Y4
12 13 14
B2 Y2
B3 A3
5 6 7
V
SS
Y3
8
9
10
E-91/J-83
P-E92/J84
E-1
P-E93/J85
D-4
P-E92/J84
D-1
P-E92/J84
D-1