Yamaha disklavier MX-100A, Service Manual

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LSI Data Table
YM5205 (PMAC: Memory Access Controller)
1. OVERVIEW
The PMAC contains the CPU peripheral circuit in a 64-pin OIL LSI. It selects addresses in and refreshes
the dynamic RAM and also makes communication between the dynamic RAM and the FDC possible in
the DMA mode. The other functions of PMAC include interrupt generation using an internal timer,
decoding addresses for ROM I/O operations and FDC, CPU clock extension for low speed I/O access,
generation of FDC, and write precompensation for the floppy disks.
To use the PMAC, the system must include a 2MHz YM2002CPU, the MB8877 FDC, MB8116Hx
8 (16KBytes) RAMs, and 2732-35x2 (8KBytes) ROMs. For future extensions, however, one can use
16KByte ROMs and 64KByte RAMs.
Use of PMAC assures the following:
Almost total elimination of the random logic involving DMAC (LSI) and CPU.
Reduction in the overheads caused due to DMA and memory refreshings because PMAC supervises
the CPU operation clock.
YM5205 Block Diagram
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