Yaesu FT-857 series, Technical Supplement

Page: 11 / 82

11
Circuit Description
PLL Frequency Synthesizer
The PLL Frequency Synthesizer consists mainly of the
master reference oscillator circuit, 2nd local oscillator cir-
cuit, PLL IC, and CAR-DDS and REF-DDS units, which
digitally synthesize carrier outputs, plus a PLL circuit
which contains a voltage controlled oscillator (VCO).
Master Reference Oscillator Circuit
The master reference oscillator uses a Crystal Oscillator
(oscillation frequency: 22.625 MHz) composed of
Q5001
(
2SC4400-4
), X5001 , TC5001, C5001, and R5005. The
reference oscillator signal passes through a buffer ampli-
fier
Q5002 (
2SC4400-4
), and is then fed to the MAIN
Unit via J5002.
CAR-DDS Circuit REF-DDS Circuit
DDS ICs Q 1 0 6 2 (
A D 9 8 3 5 B R U
) , a n d Q 2 0 1 6
( AD9850BAS ) each contain a shift register, selector,
phase accumulator, and ROM. The reference oscillation
frequency (22.625 MHz) that is delivered to each of the
DDS Units is applied to each DDS IC after amplification
by transistors
Q1043 , Q1046 , Q1048 , and Q1059 (all
2SC4400-3
).
The DDS outputs contain digital amplitude data corre-
sponding to serial frequency data from CPU IC
Q1049 .
The DDS frequency range is 453.5 ~ 466.5 kHz (center
frequency = 455.0 kHz) for the CAR-DDS, and 7.2-8.0
MHz for the REF DDS.
1st Local Oscillator Circuit
VCO output is buffer-amplified by Q2011 ( 2SC5374 )
and Q2022 (
UPC2713T
), and passes through a low-pass
filter. It is then fed to the TX/RX frequency mixer cir-
cuitry of the MAIN Unit.
2nd Local Oscillator Circuit
The 2nd LO circuit is a Hartley-type overtone oscillator
circuit (frequency: 67.875 MHz) composed of
Q1052
( 2SC4400-3 ) on the MAIN Unit.
PLL Circuit
The PLL circuit is a frequency mixing type composed of
a VCO, mixer, PLL IC, and loop filter. The VCO consists
of five circuits (VCO1, VCO2, VCO3, VCO4 and VCO5),
with a frequency range of 68.430-538.330 MHz divided
into five bands, allocated to the five VCO circuits. VCO1-
VCO5 consist mainly of FETs
Q2004 , Q2005 , and Q2006
(all
2SK210GR
); transistors Q2009 and Q2010 (both
2SC5374 ); diodes D2001 - D2006 (all HVC362 ), D2007
(
1SV282
), D2008 (
1SV281
), and D2009 (
1SV286
); and
coils T2001-T2003, L2010, and L2011.
The VCO switching signal from the connector J2002 is
used to drive switching transistors
Q2001 , Q2002 , Q2003 ,
Q2012 , and Q2013 (all DTC124EU ) to switch the source
terminal of the oscillator FET.
The 68.430-538.330 MHz VCO signal is buffer-ampli-
fied by
Q2023 (
UPC1688G
), and fed to PLL IC Q2021
(
FQ7925
).
The REF-DDS signal (7.2-8.0 MHz) is fed to PLL IC
Q2021 after it passes through a low-pass filter composed
of C2064, C2067, C2069, C2071, C2075, L2014, L2015,
and L2016, and is fed to PLL IC
Q2021 (
FQ7925
). The
phase of the reference frequency and that of the signal
input to the PLL IC are compared, and a signal whose
pulse corresponds to the phase difference is produced.