Xycom XVME-653, Manual

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XVME-653/658 Manual
2-6
Register 233h – Watchdog Timer Port
This register controls watchdog timer operation.
Table 2-10 Watchdog Timer Port Register Settings
Bit Signal Result
0 RESERVED Reserved
1 RESERVED Reserved
2 RESERVED Reserved
3 RESERVED Reserved
4 WDOG_EN Enables the watchdog timer
5 MRESET_EN Timeout generates reset when asserted
6 WDOG_STS Watchdog timer status bit
7 WDOG_CLR Clears the watchdog timer
Register 234h – NVRAM and DiskOnChip Port
This register controls access to either the NVRAM or the DiskOnChip (DOC) compo-
nent. Bits 7 and 8 also control the byte swapping on XVME-653/658 modules that are
equipped with byte-swapping hardware. In XVME-653/30x modules without byte-
swapping hardware, bits 7 and 8 are RESERVED.
Table 2-11 NVRAM and DiskOnChip Port Register Settings
Bit Signal Result
0 Control ROM/RAM15 ROM address 15 - page control bit
1 Control ROM/RAM16 ROM address 16 - page control bit
2 Control ROM/RAM17 ROM address 17 - page control bit
3 DOC enable Enables DOC mode
4 Range select 0
5 Range select 1
6 SWAPS 1 = No swapping (data invariant) occurs during Slave cycles
(This byte can only be set for byte-swapping modules.)
7 SWAPM 1 = No swapping (data invariant) occurs during Master cycles
(This byte can only be set for byte-swapping modules.)
The following ranges are defined by bits 4 and 5 in register 234h.
Table 2-12 Register 234h Defined Ranges
Range Select Bits Range
00 No range
01 CC000-CFFFF
10 D0000-D7FFF
11 D8000-DFFFF