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XVME-212 Manual
August, 1989

Signal

Mnemonic

A0l-A23

A24-A31

BBSY*

BCLR*

BERR*

BGOIN*-
BG3IN*

BG0OUT*-

BG3OUT*

Table

B-l.

VMEbus Signal Identification (cont’d)

Connector

and

Pin Number

1A:24-30
lC:l5-30

2B:4-11

1B:l

lB:2

1C:ll

1 B:4,6,

8,l0

1 B:5,7,

9,ll

Signal Name and Description

ADDRESS BUS (bits l-23): Three-state driven address lines
that specify a memory ‘address.

ADDRESS BUS (bits 24-31): Three-state driven bus
expansion address lines.

BUS BUSY: Open-collector driven signal generated by the
current DTB master to indicate that it is using the bus.

BUS CLEAR: Totem-pole driven signal generated by the
bus arbitrator to request release by the DTB master if a
higher level is requesting the bus.

BUS ERROR: Open-collector driven signal generated by a

slave. It indicates that an unrecoverable error has occurred
and the bus cycle must be aborted.

BUS GRANT (0-3) IN: Totem-pole driven signals generated

by the Arbiter or Requesters. Bus Grant In and Out signals
form a daisy-chained bus grant. The Bus Grant In signal
indicates to this board that it may become the next bus

master.

BUS GRANT (0-3) OUT: Totem-pole driven signals
generated by Requesters.

These signals indicate that a

DTB master in the daisy-chain requires access to the bus.

B-2

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Summary of Contents for 74212-001B

Page 1: ...rutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective owner...

Page 2: ...O 1997 XYCOM INC Digital Input Module PIN 74212 001B Printed in the United States of America Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...pyrighted by Xycom Incorporated Xycom and shall not be reproduced or copied without expressed written authorization from Xycom The information containedwithin this document is subject to change without notice xycom Technical Publications Department 750 North Maple Road Saline MI 48176 1292 313 429 4971 phone 313 429 1010 fax Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE...

Page 4: ...l Switches S2 2 8 IACK Enable Jumpers Jl J2 2 8 Debounce Period Jumpers 54 511 2 9 Installation 2 9 Installation Procedure 2 11 Digital Input Connections 2 11 Mechanical Switch Relay Operation 2 13 XVME 21211 2 13 XVME 212 2 2 13 PROGRAMMING Introduction 3 1 Base Addressing 3 1 1 0 Interface Block 3 3 Module Identification Base OlH to 3FH 3 3 Extended Status and Status Control Registers 3 5 Extend...

Page 5: ...h Bank S1 Base Address Switches 2 5 VMEbus Chassis 2 10 XVME 212 1 0 Interface Block and its Possible 3 2 Locations in Short 1 0Address Space Extended Status and Status Control Registers 3 5 Data Registers read only 3 9 Change Registers read only 3 10 Generating a VMEbus Interrupt 3 12 Relationship of Input Channel Signals with 3 14 Respect to Stopping the Scanner LIST OF TABLES TITLE PAGE XVME 2 ...

Page 6: ... TITLE Privilege Options Address Modifier Code Options Interrupt Level Switches S2 IACK Enable Jumpers Debounce Period Jumpers Input Connector Signal Definitions Identification Data LED Status PAGE Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 7: ... other than the 12V may be applied to the inputs within the l0V 50V input range however some board modification will be necessary i e cutting the well identified and easily accessible PC traces to the 12V on board supply XVME 212 2 The 2 version of the XVME 212 is very similar to the I version except for the range of allowable input voltage and the absence of an on board 12V DC power supply The XV...

Page 8: ...ramming of Xycom VMEbus 1 0 modules simple and consistent The following features apply to the operation of the XVME 212 Module address space The XVME 212 and all VMEbus modules are controlled by writing to addresses within the 64K Short 1 0 Address space A VMEbus module can be switched to occupy any of the 64 available 1K blocks This block known as the 1 0 Interface Block contains all of the modul...

Page 9: ...2 l I I 5OV DC max Logic 1 10 to 5OV DC Logic 0 0 to lV DC Typical threshold 3V DC Input Voltage Range XVME 212 2 65V DC max Logic 1 2 to 6 5V DC Logic 0 0 to 0 8V DC Typical threshold 1 2V DC 1 Input Impedance XVME 2 12 1 3 9K 5 Input Impedance XVME 2 12 2 330 5 Propagation Delay with fastest debounce selected Of f to on 100 usec max l0 25 usec typ On to off 600 usec max 150 usec typ Minimum Dete...

Page 10: ...ing Extremely low humidity conditions may require special protection against static discharge Altitude Operating Non operating Vibration Operating Sea level to 20 000 ft 6096m Sea level to 50 000 ft 15240m 5 to 2000 Hz O 15 peak to peak displacement 2 5g peak acceleration Non operating 5 to 2000 Hz 030 peak to peak displacement 5 0 g peak maximum acceleration Shock Operating 30 g peak acceleration...

Page 11: ...tandard l Al 6 D16 Data transfer bus slave l Base address jumper selectable within 64K short I O address space l Occupies 1K consecutive byte locations l I 1 to I 7 Interrupter STAT with programmable vector l Includes Xycom s standard I O module interface l NEXP 1 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 12: ...ents for operation of the XVME 212 are one of the following either A or B below A A host processor properly installed on the same backplane A properly installed controller subsystem An example of such a control subsystem is the Xycom XVME 010 System Resource Module OR B A host processor which incorporates an on board controller subsystem 2 3 LOCATION OF COMPONENTS RELEVANT TO INSTALLATION The jump...

Page 13: ...al August 1989 mmmm mmmm 1 I J4 J5 J6 J7 J8 J9 JIO JII L COMPONENT SIDE Figure 2 1 XVME 212 jumpers switches and connectors Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 14: ...selected by switches l 6 of the Address Switches Sl Privilege level required to access the module selected by Switch 7 of the Address Switches Sl VMEbus interrupt level selected by the Interrupt Level Switches S2 Whether to use or bypass the IACK daisy chain selected by Jumpers Jl and J2 Debounce Period Jumpers The length of the debounce period is selected by Jumpers J4 and Jl1 2 3 Artisan Technol...

Page 15: ...ain J3 This jumper works in conjunction with Sl Switch 8 for address space selection i e Short I O Address Space or Standard Address Space See note below J4 Jll Determines the debounce period Note See also Section 2 4 2 Switch 8 of Switch Bank Sl 2 4 1 Base Address Selection Switches Sl 1 to Sl 6 The XVME 212 module is designed to be addressed within either the VMEbus Short I O or Standard Memory ...

Page 16: ...2 shows the Switch bank S1 and how the individual switches 1 6 relate to the base address bits Figure 2 2 Switch Bank S1 Base Address Switches When a switch is in the closed position i e when it is pushed in on the opposite end of the switch bank from the open label the corresponding base address bit will be logic 0 When a switch is set to the open position the corresponding base address bit will ...

Page 17: ...h NOOH 3400h 3800H 3c00h 4000H 4400H 4800H 4c00h MOOH 5400h 5800H 5c00h 6000H 6400H 6800H 6c00h 7000H 7400H 7800H 7c00h 8000H 8400h 8800H 8c00h 9000H 9400H 9800H 9c00h AOOOH A400H ASOOH ACOOH BOOOH MOOH 8800H BCOOH COOOH C400H C800H CCOOH DOOOH D400H D800H DCOOH EOOOH e400h E800H ECOOH FOOOH f400h F800H FCOOH Open Logic I Closed Logic 0 2 6 Artisan Technology Group Quality Instrumentation Guarante...

Page 18: ...dard Address Space Note that in this mode the XVME 212 will always reside within the upper 64 Kbyte segment of the Standard Memory Address Space i e the address range FF0000H through FFFFFFH Sl switches 1 through 6 then determines which 1K block of the upper 64 Kbyte segment is to be occupied 2 4 3 Supervisory Non Privileged Mode Selection The XVME 212 can be configured to respond only to supervis...

Page 19: ...2 S2 3 OPEN OPEN OPEN OPEN CLOSED CLOSED CLOSED S2 2 OPEN OPEN CLOSED CLOSED OPEN OPEN CLOSED S2 1 OPEN CLOSED OPEN CLOSED OPEN CLOSED OPEN VMEbus Interrupt Level 7 6 5 4 3 2 1 None interrupts disabled 2 4 6 IACK Enable Jumpers Jl J2 When operating in an interrupt environment the module uses the VMEbus IACK daisy chain to determine which module gets acknowledged if two or more modules share one of...

Page 20: ...ration of time T the change will be reported to the scanner at the end of time period T This means that the input must assume the new state and stay in the new state without bouncing for time T before the change is reported to the scanner The value of time T is selectable via eight on board jumpers One and onlv one jumper must be installed This jumper defines the time T to be used by all 32 channe...

Page 21: ...f backplane connectors are depicted the P1 backplane and the P2 backplane However the XVME 212 uses only the P1 backplane PI BACKPLAN GUIDE SLOT SOLDER SIDE I N XP VME BOARD P2 BACKPLAN Figure 2 3 VMEbus Chassis 2 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 22: ... connector engage the board should slide freely in the plastic guides 4 Apply straightforward pressure to the handle on the panel front until the connector is fully engaged and properly seated NOTE It should not be necessary to use excessive force or pressure to engage the connectors If the board does not properly connect with the backplane remove the module and inspect all connectors and guide sl...

Page 23: ... CH2 CH18 CH2 CH18 CH3 CH19 CH3 CH19 CH4 CH20 CH4 CH20 CH5 CH21 CH5 CH21 CH6 CH22 CH6 CH22 CH7 CH23 CH7 CH23 CH8 CH24 CH8 CH24 CH9 CH25 CH9 CH25 CHl0 CH26 CHlO CH26 CHIl CH27 CHll CH27 CH12 CH28 CH12 CH28 CH13 CH29 CH13 CH29 CH14 CH30 CH14 CH30 CH15 CH31 CH15 CH31 12V Return XVME 212 l 12V Return XVME 212 l Ground XVME 2 12 2 Ground XVME 2 12 2 12V Return XVME 212 l 12VReturn XVME 212 l Ground XVM...

Page 24: ...tion applies onlv to channels which have their break point cut The 300V channel to VMEbus isolation is maintained whether the break points are cut or not because the 12V supply is isolated to 300V 2 7 2 XVME 212 2 With the XVME 212 2 the 5V supply of the VME backplane is used with the mechanical switches Each terminal of the input channels is connected to 5V with reference to logic ground while pi...

Page 25: ...escribed in Section 2 4 1 located in the 64K Address space It this address space When located at its base address the XVME 212 is allotted a 1K block of address space for its own use This 1K block of address space is termed the I O Interface Block and contains all of the module s programming locations Figure 3 l shows the I O Interface Block of the XVME 212 and its relation to the address space Wh...

Page 26: ...upt Ack Vector read only 7FH 81H readlwrite 83H write only Undefined Undefined 8BH read only 8DH 8FH I Data Register 0 Data Register 2 Change Register 0 Figure 3 1 XVME 212 110 Interface Block and its Possible Locations in Short 1 0 Address Space Data Register 1 Data Register 3 Change Register 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 27: ...ch hold the data from the four ports Change registers which indicate whether data on any channel has changed Note Reading or writing to undefined locations may make application software incompatible with future versions of this module 3 4 MODULE IDENTIFICATION DATA Base 0lH to 3FH odd byte locations only The Xycom module identification scheme provides a unique method of registering module specific...

Page 28: ... always XYC for XYCOM modules 3 characters Module Model Number 3 characters and 4 trailing blanks Number of IK byte blocks of 110 space occupied by this module 1 character Major functional revision level with leading blank if single digit Minor functional revision level with trailing blank if single digit Manufacturer Dependent Information Reserved for future use Artisan Technology Group Quality I...

Page 29: ...ound sequentially at locations 101lH 1013H 1015H 1017H 1019H IOlBH and 10lDH 3 5 EXTENDED STATUS base 80H and STATUS CONTROL REGISTERS base 81H Writing to the Status Control Register controls the red and green LEDs enables disables interrupts from any of the four ports and indicates whether or not an interrupt is pending k base 080H base 081H 4 Red LED SYSFAIL Green LED LL VMEbus Interrupt Pending...

Page 30: ... test 2 Note The XVME 212 is a non intelligent module so all diagnostics must be performed by the system host VMEbus Interrupt Pendinq This read only bit reads 1 whenever BOTH of the following conditions are met One or more of the Change Register n Interrupt Enable bits bits 4 7 of the Status Control Register has been set to 1 AND A bit in one of the interrupt enabled Change Registers associated w...

Page 31: ...et Writing a 1 in one of these bits enables interrupts from a specific Change Register writing 0 disables interrupts from the register Bit 4 Enables disables Change Register 0 Bit 5 Enables disables Change Register 1 Bit 6 Enables disables Change Register 2 Bit 7 Enables disables Change Register 3 3 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 32: ...errupts Bits 4 7 of the Status Control Register are individually ANDed with bits 8 11 The results of the ANDs are ORed together to produce bit 2 Bit 2 is ANDed with bit 3 and when the result of this AND is 1 a VMEbus interrupt will be generated The level of the VMEbus interrupt is determined by the setting of Switch bank S2 see Section 2 4 5 Section 3 8 describes in detail how interrupts are gener...

Page 33: ...s This is the only mechanism with the exception of VMEbus resets which will reset the Change Register bits Each Change Register bit will be set again when the input state is different from the image in the Data Registers This alerts the CPU that an input has changed state since the CPU last read the Data Registers because the Change Register was zeroed the last time the Data Register was read The ...

Page 34: ...ibble four inputs at a time for state transitions Eight nibbles 32 input channels must be checked to complete one scan The architecture of the scanner does not allow it to be stopped in the middle of a scan The scanner must complete its scan and stop before meaningful information can be read from the Data or Change registers The assertion of DTACK is delayed until the scanner completes its scan an...

Page 35: ...n the Status Control Register bits 4 7 When this bit is set a VMEbus interrupt will be generated when any bit of the corresponding Change Register is set and the VMEbus Interrupt Enable bit bit 3 of the Status Control Register is set This alerts the CPU that an input has changed state since the last time the CPU read the data registers Figure 3 5 illustrates the logic involved in generating a VMEb...

Page 36: ...it 7 33 Bit3 NOTE The numbered bits are located in the Extended Status and Status Control Registers base 080H See Figure 3 2 VMEbus Interrupt Figure 3 5 Generating a VMEbus Interrupt Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 37: ...ord 2 read Data Registers 0 and 1 as one word 3 read Change Registers 2 and 3 as one word 4 read Data Registers 2 and 3 as one word During the time that the scanner is stopped no changes in state will be detected and the Data Registers are not updated In systems which must keep up with the fast changing inputs the time that the scanner is stopped must be minimized It is therefore necessary to read...

Page 38: ...t Channel Signals with Respect to Stopping the Scanner The Data and Change Registers contain the following data at the end of the designated scan After scan n n 1 n 2 n 3 Change Register read at point A Data Register read at point B Change Register bits X Y z 0 0 0 0 1 0 1 0 0 1 0 0 Data Register bits X Y z 1 0 0 1 1 0 0 1 0 1 1 0 Please note the following 1 The pulse on line z was undetected beca...

Page 39: ...he Data or Change Registers directly It is not necessary to read the Change Registers at all if the user is not concerned about which individual bit in the change register is set In these cases the user would simply read the Data Registers when the module generated an interrupt in interrupt driven environments or when the status bits 8 11 indicate a change has occurred in polled environments 3 12 ...

Page 40: ...e determine the operational condition of specific modules within the system 4 Interrupt Control How software is able to control and monitor the capability of the module to interrupt the system 5 Communication between Modules How master host processors and intelligent I O modules communicate through shared global memory or the dual access RAM on the modules 6 The I O Kernel How intelligent and non ...

Page 41: ...rements Figure A 1 shows an abbreviated view of the short 1 0 memory short 1 1 0 Address Space Base Address Jumper Options Jumpers J8 57 J5 5 4 A13 A12 A l l AIO IN IN IN IN IN IN IN OUT IN IN OUT IN IN IN OUT OUT IN OUT IN IN IN OUT IN OUT IN OUT OUT IN IN OUT OUT OUT OUT IN IN IN OUT IN IN OUT OUT IN OUT IN OUT IN OUT OUT OUT OUT IN IN OUT OUT IN OUT OUT OUT OUT IN OUT OUT OUT OUT Module base od...

Page 42: ...dule holds specific I O status data and pointer registers for use with IPC protocol All intelligent XVME I O modules have an area of their I O Interface Blocks defined as dual access RAM This area of memory provides the space where XVME slave I O modules access their command blocks and where XVME master modules could access their command blocks i e master modules can also access global system memo...

Page 43: ...information in an ASCII encodedi ormat The ITD data is provided as 32 ASCII encoded characters consisting of board type manufacturer identification module model number number of 1 Kbyte blocks occupied by the module and model functional revision level information This information can be studied by the system processor on power up to verify the system configuration and operational status Table A 1 ...

Page 44: ...y necessary to use odd backplane addresses to access the I D data Thus each of the 32 bytes of ASCII data has been assigned to the first 32 odd 1 0 Interface Block bytes odd bytes 1H 3FH The I D information can be accessed by addressing the module base offset by the specific address for the character s needed For example if the base address of the board is jumpered to 1000H and access to the modul...

Page 45: ...states for the module test conditions on both the intelligent 1 0 modules and the non intelligent 1 0 modules Red LED 1 Green LED FRONT VIEW XXXX XVME XXX FAIL TEST w PASS Status Bits LEDs 3 2 1 0 Green Red 0 0 0 0 OFF ON 1 0 0 0 OFF ON 0 0 0 1 OFF OFF 0 1 1 0 ON ON 1 1 1 1 ON OFF all others X X SYSFAIL Status ON Module not yet tested ON Module failed test OFF Inactive module ON Module undergoing ...

Page 46: ...ntelligent XVME I O modules the status control register is used to indicate the state of the front panel LEDs and to set and verify module generated interrupts The LED status bits are Read Write locations which provide the user with the indicators to accommodate diagnostic software The Interrupt Enable bit is also a Read Write location which must be written to in order to enable module generated i...

Page 47: ... Write Green LED 0 Green LED Off 1 Green LED On 2 Read Only Interrupt Pending 0 No Interrupt 1 Interrupt Pending 3 Read Write Interrupt Enable 0 Interrupts Not Enabled 1 Interrupts Enabled Bit Intelligent Modules 0 Read Only Red LED 0 Red LED ON 1 Red LED Off 1 Read Only Green LED 0 Green LED Off 1 Green LED On 2 3 Read Only Test Status Indicators Bit 3 Bit 2 0 0 Self test not started 0 1 Self tes...

Page 48: ...f a standard kernel combined with module dependent application circuitry Module standardization results in more efficient module design and allows the implementation of the Standard I O Architecture The biggest benefit of standardization for intelligent modules is that it allows the use of a common command language or protocol Interprocessor Communication Protocol in this case The intelligent kern...

Page 49: ...llector driven signal which indicates that the AC input to the power supply is no longer being provided or that the required input voltage levels are not being met INTERRUPT ACKNOWLEDGE IN Totem pole driven signal IACKIN and IACKOUT signals form a daisy chained acknowledge The IACKIN signal indicates to the VME board that an acknowledge cycle is in progress INTERRUPT ACKNOWLEDGE OUT Totem pole dri...

Page 50: ...e driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus BUS ERROR Open collector driven signal generated by a slave It indicates that an unrecoverable error has occurred and the bus cycle must be aborted BUS GRANT 0 3 IN Totem pole driven signals generated by the Arbiter or Requesters Bus Grant In and Out signals form a daisy cha...

Page 51: ...rd transfers that a data transfer will occur on data buss lines D00 D07 DATA STROBE 1 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines D0 D1 5 DATA TRANSFER ACKNOWLEDGE Open collector driven signal generated by a DTB slave The falling edge of this signal indicates that valid data is available on the data bus during a read cyc...

Page 52: ...signals generated by an interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal indicates that the current transfer is a 32 bit transfer RESERVED Signal line reserved for future VMEbus enhancements This line must not be used A reserved signal which will be used as the clock for a serial communication bus protocol which is still ...

Page 53: ...e system to be reset WRITE lA 14 WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high level indicates a read operation a low level indicates a write operation 5V STDBY lB 31 5 VDC STANDBY This line supplies 5 VDC to devices requiring battery backup 5V 1 A 32 5 VDC POWER Used by system logic circuits lB 32 1C 32 2B 1 13 32 12V 12v 1C...

Page 54: ... system to be reset WRITE lA 14 WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high level indicates a read operation a low level indicates a write operation 5V STDBY lB 31 5 VDC STANDBY This line supplies 5 VDC to devices requiring battery backup 5V 1 A 32 5 VDC POWER Used by system logic circuits 1B 32 1C 32 2B 1 13 32 12V 12V lC ...

Page 55: ...Mnemonic DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 GND SYSCLK G N P DSl DSO WRITE GND DTACK GI AS GND IACK IACKIN IACKOUT AM4 A07 A06 A05 A04 A03 A02 A0 1 12v 5v in Assignments Row B Signal Mnemonic BBSY BCLR ACFAW BGOIN B G O O T BGlIN B G I O T BG2IN B G O T BG3IN BG QUT BRO BR1 BR2 BR3 AM0 AM1 AM2 AM3 GND SERCLK 1 SERDAT 1 GND IRQ7 IRQ6 IRQS IRQ4 IRQ3 IRQ2 IRQ1 5V STDBY 5v Row C Signal Mnemonic GND SYSFV...

Page 56: ... Block Diagram CHANNELS CHANNELS I CONNECTORJK1 I I CONNECTOR JK2 I 1 OPTICALFLATOR 1 SCANNER c CHANGE REGISTERS DATA REGISTERS I VMEbus INTERFACE I V O STANDARD INTERFACEI Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 57: ...XVME 212 Manual August 1989 Assembly Drawing JK2 I L 1 L I COMPONENT SIDE Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 58: ...1 1 r x N N N N N N N Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 59: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 60: ...DSTAT D 1 2 YRCTL D I I ERESET D 1 2 BUFENI D I 1 YRITEL D 1 1 DlTR BUS 5v 1I BUFFERS A 74LS645 1 Rev A XVME 212 DIN Schematic Sheet 3 of 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 61: ...N N N N N 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 62: ...HNGZIEN D RSTINTI I CHRNGE DETECT I I INTEN 1LEVl BRl ILEVl on2 ILEVZ BR3 S I N 1 BDSl BOSO VRVEC HZ IPEN 3 LINT 3 DEBOUNCE CLOCK GENEROTOR IRCK VECTOR nYLEv 2 a OCLK 6 7 Rev A CLOCK DRIVER XVME 212 DIN Schematic Sheet 5 of 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 63: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 64: ...W N Z Z l Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 65: ...dule Identification Data Extended Status 8AH I Data Register 2 I Data Register 3 Status Control Undefined 8CH 8EH read only 83H write only Change Register 0 Change Register 2 8BH read only 8DH 8FH I Change Register 1 Change Register 3 Figure D 1 XVME 212 1 0 Interface Block and its Possible Locations in Short 1 0 Address Space Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOUR...

Page 66: ...EN OPEN CLOSED CLOSED CLOSED CLOSED S2 2 OPEN OPEN CLOSED CLOSED OPEN OPEN CLOSED CLOSED S2 1 OPEN CLOSED OPEN CLOSED OPEN CLOSED OPEN CLOSED VMEbus Interrupt Level 7 6 5 4 3 2 1 None interrupts disabled Jumpers Use Uselbypass IACK daisy chain 51 52 B B Module uses IACK daisy chain A A Module bypasses chain Must be in B position to select the Short 110 Address space J4 J11 These jumpers determine ...

Page 67: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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