13
B3
SCL
I2Cbus clock
P4
G_2
AV2 blue input
K2
VGA-R1
VGA(red)
R1
CVBS_1
TV composite video signal input
K1
VGA-G1
VGA(greed)
R2
Y_1
S-VHS brightness signal input
L1
VGA-SOG1 VGA(greed sync signal)
R3
CVBS_SOG1
TV composite video signal greed sync
input
M1
VGA-B1
VGA(blue)
R4
C_1
S-VHS chrominance signal input
T1 VGA_H VGA(H-sync
signal)
B9 GVBI
Vertical blanking blank
T3
VGA_V
VGA(V-sync signal)
E16
G_VS
V-SYNC output
N1
R_1
AV1 red input
F14
G_HS
H-SYNC output
N1
G_1
AV1 greed input
F15
G_AHS
H-SYNC of non-processing
N3
SOG_1
AV1 greed sync input
G15
G_DLK
Clock output
N4
B_1
AV1 blue input
GBE(0-7)
blue even pixel data output
GBO(2-9)
Blue odd pixel data output
GGE(0-7)
greed even pixel data output
GGO(2-9)
greed odd pixel data output
GRE(0-7)
red even pixel data output
GRO(2-9)
red odd pixel data output
3. PW218
PWE218 is highly quality SOC picture processing chip, it contain Scaling and Deinterlacing
functions.
Internal Block Diagram
Summary of Contents for LC-42T17
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