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XC-1A Hardware Manual (1.2)

10/18

6

Prototyping Area [F]

The XC-1A provides a 0.1” pitch plated through hole area for adding components to

the card.

The routing of I/O and power pins in the prototyping area is shown below.

3V3

X0D39

GND

GND

X0D38
X0D37
X0D36
X0D33
X0D32
X0D31
X0D30
X0D29
X0D28
X0D27
X0D26
X0D11
X0D10
X0D1
X0D0

5V

The prototyping area provides a bank of 16 I/O pins, which are mapped to the ports

on processor 0 as described in the table below.

Pin

Port

Processor

1b

4b

8b

0

X0D26

P4E0 P8C0

Prototyping
Area

X0D27

P4E1 P8C1

X0D28

P4F0 P8C2

X0D29

P4F1 P8C3

X0D30

P4F2 P8C4

X0D31

P4F3 P8C5

X0D32

P4E2 P8C6

X0D33

P4E3 P8C7

X0D36

P1M0

X0D37

P1N0

X0D38

P1O0

X0D39

P1P0

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Summary of Contents for XC-1A

Page 1: ...XC 1A Hardware Manual Version 1 2 Publication Date 2010 04 27 Copyright 2010 XMOS Ltd All Rights Reserved...

Page 2: ...the card A G C C C C C B B B B B B B B B B B B F E E E E D D D D A XS1 G4 Device B Twelve Red Green User LEDs C Four Green User LEDs D Four Push Button Switches E Four I O Expansion Areas F Prototypi...

Page 3: ...ne 16 way I O expansion header 16 I O bits Processor 3 Three red green LEDs Two 16 way I O expansion headers 16 I O bits The processors have ports that are directly connected to the I O pins Examples...

Page 4: ...1 bit ports 1E for green 1F for red on processor 0 The schematic for the clock LEDs is shown below I II III IIII V VI VII VIII IX X XI XII X1D40 PORT_CLOCKLED_1 PORT_CLOCKLED_2 PORT_CLOCKLED_3 PORT_C...

Page 5: ...PORT_CLOCKLED_1 IV X1D41 P8D5 PORT_CLOCKLED_1 V X1D42 P8D6 PORT_CLOCKLED_1 VI XCore2 X2D40 P8D4 PORT_CLOCKLED_2 VII X2D41 P8D5 PORT_CLOCKLED_2 VIII X2D42 P8D6 PORT_CLOCKLED_2 IX XCore3 X3D40 P8D4 POR...

Page 6: ...four pins which are mapped to ports as described in the table below Pin Port Processor 4b 8b 0 X0D16 P4D0 P8B2 PORT_BUTTON A X0D17 P4D1 P8B3 PORT_BUTTON B X0D18 P4D2 P8B4 PORT_BUTTON C X0D19 P4D3 P8B5...

Page 7: ...D3 X1D1 5V X1D10 X1D8 X1D6 3V3 X1D4 X1D2 X1D0 GND X2D11 X2D9 X2D7 GND X2D5 X2D3 X2D1 5V X2D10 X2D8 X2D6 3V3 X2D4 X2D2 X2D0 X3D0 X3D2 X3D4 3V3 X3D6 X3D8 X2D10 5V X3D1 X3D3 X3D5 GND X3D7 X3D9 X3D11 GND...

Page 8: ...P4B1 P8A3 P16A3 X2D6 P4B2 P8A4 P16A4 X2D7 P4B3 P8A5 P16A5 X2D8 P4A2 P8A6 P16A6 X2D9 P4A3 P8A7 P16A7 X2D10 P1C0 X2D11 P1D0 XCore3 X3D0 P1A0 X3PortA X3D1 P1B0 X3D2 P4A0 P8A0 P16A0 X3D3 P4A1 P8A1 P16A1 X...

Page 9: ...4 I XLA4 O XLA4 I XnD2 XLA3 I XLA3 O XLA3 I XnD3 XLA2 I XLA2 O XLA2 I XnD4 XLA1 I XLA1 I XLA1 I XLA1 O XLA1 I XLA1 I XnD5 XLA0 I XLA0 I XLA0 I XLA0 O XLA0 I XLA0 I XnD6 XLA0 O XLA0 O XLA0 O XLA0 I XLA...

Page 10: ...37 X0D36 X0D33 X0D32 X0D31 X0D30 X0D29 X0D28 X0D27 X0D26 X0D11 X0D10 X0D1 X0D0 5V The prototyping area provides a bank of 16 I O pins which are mapped to the ports on processor 0 as described in the t...

Page 11: ...e generated by filtering pulse width modulated PWM digital signals to form an analogue waveform which is amplified and sent to the speaker as shown below X0D34 FILTER AMPLIFIER SPEAKER The speaker pin...

Page 12: ...e XS1 G4 can then be put into JTAG mode by the PC which then boots another program No UART hardware is provided Instead two UART pins are mapped to ports as shown in the table below Pin Port Processor...

Page 13: ..._SPI_MOSI The Tools include the XFLASH utility for programming compiled programs into the flash memory XC 1A designs may also access the flash memory at run time by interfacing with the above ports 11...

Page 14: ...ELG PORT_SPEAKER PORT_BUTTON A D PORT_BUTTONLED A D USB 20MHz XTO PORT_UART_RX RST PSU System Services A Processor 1 A Processor 2 A Processor 3 B 5V PORT_SPI_MISO PORT_SPI_SS PORT_SPI_CLK PORT_SPI_MO...

Page 15: ...4 BUTTONLED C XnD21 P4C3 P8B7 P16A15 BUTTONLED D XnD22 P1G0 TESTPOINT XnD23 P1H0 UART_TX XnD24 P1I0 UART_RX XnD25 P1J0 TESTPOINT XnD26 P4E0 P8C0 P16B0 PROTO_AREA_4 XnD27 P4E1 P8C1 P16B1 PROTO_AREA_5 X...

Page 16: ...dentifiers for all processors Processor Port Location Generic Identifier 0 XS1_PORT_1A PORT_SPI_MISO XS1_PORT_1B PORT_SPI_SS XS1_PORT_1C PORT_SPI_CLK XS1_PORT_1D PORT_SPI_MOSI XS1_PORT_1E PORT_CLOCKLE...

Page 17: ...language The XMOS XS1 Architecture 3 provides an overview of the XS1 instruction set architecture The most up to date information on the XC 1A including board schematics and product datasheets is ava...

Page 18: ...n relation to its use XMOS Ltd makes no representation that the Information or any particular implementation thereof is or will be free from any claims of infringement and again shall have no liabilit...

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