Xilinx ZCU102, User Manual

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ZCU102 Evaluation Board User Guide www.xilinx.com 43
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
Clock Generation
The ZCU102 board provides fixed and variable clock sources for the XCZU9EG MPSoC.
Table 3-12 lists the source devices for each clock.
Table 3-13 lists the source devices for each clock.
Table 3-12: ZCU102 Board Clock Sources
Clock Name Frequency Clock Source
Fixed Frequency Clocks
PS_REF_CLK 33.33 MHz
U69 SI5341B Clock Generator
CLK_74_25 74.25 MHz
CLK_125 125 MHz
GTR_REF_CLK_PCIE
100 MHz
PCIE_SLOT_CLK 100 MHz
GTR_REF_CLK_SATA 125 MHz
GTR_REF_CLK_USB3 24 MHz
GTR_REF_CLK_DP
27 MHz
Programmable Frequency Clocks
USER_SI570 300 MHz (Default) U42 SI570 I2C PROG. OSC.
USER_MGT_SI570
156.2 MHz (Default)
U56 SI570 I2C PROG. OSC.
USER_MGT_SMA User-Provided Source J79 (P)/J80 (N) SMA CONN.
HDMI_SI5324_OUT Variable U108 Clock Recovery
SFP_SI5328_OUT Variable U20 Clock Recovery
Table 3-13: Clock Connections, Source to XCZU9EG MPSoC
Clock Source
Ref. Des. and
Pin
Schematic Net Name I/O Standard FPGA (U1) Pin
U69.59 PS_REF_CLK
(1)
U24
U69.45 CLK_125_P LVDS_25 G21
U69.44 CLK_125_N LVDS_25 F21
U69.51 CLK_74_25_P LVDS_25 AK15
U69.50 CLK_74_25_N
LVDS_25 AK14
U69.38 PCIE_SLOT_CLK_P N/A (PCIE CONNECTOR) P1.A13
U69.37 PCIE_SLOT_CLK_N N/A (PCIE CONNECTOR) P1.A14
U69.42 GTR_REF_CLK_PCIE_P
(2)
AA27
U69.41 GTR_REF_CLK_PCIE_N
(2)
AA28
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