Xilinx XtremeDSP Spartan-3A DSP 3400A HW-SD3400A-DSP-DB-UNI-G User Manual Download Page 3

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UG498 (v2.2) November 17, 2008

www.xilinx.com

Spartan-3A DSP 3400A Edition User Guide

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

6/2007

0.1

Preliminary version.

7/2007

0.2

Added appendix.

7/2007

0.3

Updated version for final review.

8/2007

1.0

• Updated FMC information.

• Updated support information.

• Added FPGA pin assignments for DDR2 interface.

• Added FPGA pin assignments for USB/System ACE interface.

9/2007

1.1

Added Known Issues section: Limitation of DDR2 clock rate to 133 MHz; Soft Touch
connector not compliant with Agilent probes; FMC connector is in violation of some
rules of the standard.

10/2007

1.2

• Updated Table 20 (Serial Port FPGA Pin Assignments) and modified layout to reflect
change in corporate image.

• Updated for XtremeDSP Spartan-3A DSP Development Board Revision D.

10/2007

2.0

Updated for XtremeDSP Spartan-3A DSP Development Board Revision.

1/2008

2.1

Updated with new clock generator configuration.

11/17/08

2.2

• Ported to Xilinx template.

• Updated Table 12 (FMC Pin G3 is attached to net 1_CLK0_C2M_N).

• Updated to account for PS6 being the power supply used for FMC 2 adjustable voltage.

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Summary of Contents for XtremeDSP Spartan-3A DSP 3400A HW-SD3400A-DSP-DB-UNI-G

Page 1: ...Platform User Guide optional UG498 v2 2 November 17 2008 optional XtremeDSP Development Platform Spartan 3A DSP 3400A Edition User Guide UG498 v2 2 November 17 2008 Downloaded from Elcodis com electronic components distributor ...

Page 2: ...tice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARR...

Page 3: ... DDR2 clock rate to 133 MHz Soft Touch connector not compliant with Agilent probes FMC connector is in violation of some rules of the standard 10 2007 1 2 Updated Table 20 Serial Port FPGA Pin Assignments and modified layout to reflect change in corporate image Updated for XtremeDSP Spartan 3A DSP Development Board Revision D 10 2007 2 0 Updated for XtremeDSP Spartan 3A DSP Development Board Revis...

Page 4: ...Spartan 3A DSP 3400A Edition User Guide www xilinx com UG498 v2 2 November 17 2008 Downloaded from Elcodis com electronic components distributor ...

Page 5: ... Bottom 40 FMC Expansion Connectors 43 DDR2 Memory 43 DDR2 Memory Expansion 43 DDR2 Clock Signal 43 DDR2 Signaling 44 MIG Compatibility 44 I2C Bus Addressing 44 Chapter 2 Configuration Options JTAG Configuration 47 JTAG Chain 47 System ACE Controller Configuration 48 Board Flash Memory Configuration 48 SPI Flash Memory Configuration 48 Chapter 3 Programming the IDT Clock Chip Downloading to the Sp...

Page 6: ...UG489 v2 2 November 17 2008 www xilinx com XtremeDSP Spartan 3A DSP User Guide Downloaded from Elcodis com electronic components distributor ...

Page 7: ... Bottom View of Spartan 3A DSP 3400A Edition Board 40 Chapter 2 Configuration Options Figure 2 1 Spartan 3A DSP 3400A Edition Board JTAG Chain 47 Chapter 3 Programming the IDT Clock Chip Figure 3 1 P2 IDT5V9885 JTAG Connector 49 Figure 3 2 Programming the IDT5V9885 on the Spartan 3A DSP 3400A Edition Board Using iMPACT 50 Figure 3 3 Programming the IDT5V9885 on the Spartan 3A DSP 3400A Edition Boa...

Page 8: ...XtremeDSP Spartan 3A DSP User Guide www xilinx com UG489 v2 2 November 17 2008 Downloaded from Elcodis com electronic components distributor ...

Page 9: ... FMC 2 Expansion Connector Pin Assignments 2 31 Table 1 13 Reset Connection Pin Assignment 32 Table 1 14 Clock Generator Default Settings 33 Table 1 15 I2C FPGA Pin Assignments 33 Table 1 16 FPGA Fan Controller Interface 34 Table 1 17 FPGA I O Bank Voltage Rail 34 Table 1 18 FPGA LCD Interface 35 Table 1 19 User defined Button FPGA Pin Assignments 35 Table 1 20 Serial Port FPGA Pin Assignments 36 ...

Page 10: ...XtremeDSP Spartan 3A DSP User Guide www xilinx com UG489 v2 2 November 17 2008 Downloaded from Elcodis com electronic components distributor ...

Page 11: ... purpose of the User Guide and the conventions used in this document Chapter 1 Introduction identifies the major components parts and functionality of the Spartan 3A DSP 3400A Edition board Chapter 2 Configuration Options provides an overview of the four configuration methods available on the FPGA on the Spartan 3A DSP 3400A Edition board Chapter 3 Programming the IDT Clock Chip provides step by s...

Page 12: ...more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option_name design_name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr...

Page 13: ... Cross reference link to a location in another document See Figure 2 5 in the Virtex II Platform FPGA User Guide Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files Convention Meaning or Use Example Downloaded from Elcodis com electronic components distributor ...

Page 14: ...14 www xilinx com Spartan 3A DSP 3400A Edition User Guide UG498 v2 2 November 17 2008 Preface About This Guide R Downloaded from Elcodis com electronic components distributor ...

Page 15: ... DSP 3400A Edition Board Block Diagram DVI RJ45 10Base T 100Base TX 1000Base T Ethernet PHY CompactFlash CPLD SPI EEPROM ZBT SRAM 256 Mb FMC 34 diff 68 se 36 FMC 34 diff 68 se USB Peripheral USB Controller USB Host Spartan 3A DSP FPGA XC3SD3400A SystemAce LCD 16x2 Pixels DDR2 SDRAM SODIMM DB9 RS232 FMC Expansion Module 2 FMC Expansion Module 1 Video Encoder Audio Codec Clock Generator I2 C EEPROM ...

Page 16: ...ustrates the parts on the top of the Spartan 3A DSP 3400A Edition board Each numbered item in the diagram is followed by a numbered description X Ref Target Figure 1 2 Figure 1 2 Top View of Spartan 3A DSP 3400A Edition Board 2 11 3 5 9 13 14 15 17 24 26 23 27 25 28 29 31 33 32 20 10 12 8 1 4 7 6 35 34 21 36 22 30 18 19 16 Downloaded from Elcodis com electronic components distributor ...

Page 17: ... in the I2C EEPROM The FPGA pins used for the USB interface are shared with the System ACE interface as identified in Table 1 1 2 USB Peripheral Port Type B connector used to connect peripheral USB devices to the Spartan 3A DSP 3400A Edition board 3 USB Host Port Type A connector used to connect a host device to the Spartan 3A DSP 3400A Edition board Table 1 1 USB System ACE Interface Pin Assignme...

Page 18: ...er device drives the digital and analog signals to the DVI connector 5 DVI Connector The display controller device is controlled through the I2C bus The DVI connector supports the I2C protocol allowing the development board to read monitor configuration parameters which can then be read by the FPGA through the I2C bus See I2C Bus Addressing page 42 for detailed information Table 1 2 AC 97 SoundMAX...

Page 19: ...de pins 2 3 or GMII mode pins 1 2 Table 1 4 defines the default configuration of the Ethernet PHY which can be modified through software Table 1 5 identifies the FPGA pin assignments for building new FPGA files Table 1 4 Default Ethernet PHY Configuration Configuration Pin Board Connection Bit 2 Bit 1 Bit 0 CONFIG0 Vcc 2 5 V PHYADR 2 1 PHYADR 1 1 PHYADR 0 1 CONFIG1 Ground ENA_PAUSE 0 PHYADR 4 0 PH...

Page 20: ...ut how to configure the adjustable power supply The Flash memory shares the same address data bus as the ZBT synchronous SRAM 12 ZBT Synchronous SRAM 11 PS 2 Connectors The Spartan 3A DSP 3400A Edition board is equipped with two PS 2 connectors one each for a keyboard and mouse Bi directional level shifting transistors allow the 1 8 V I O to interface with the 5 V I O of the PS 2 connectors which ...

Page 21: ...RAM Make sure that FMC 1 adjustable power supply is configured for 3 3V to use the memory See 14 FMC Expansion Connector 1 for information about configuring the adjustable power supply 13 Soft Touch Connector The Soft Touch connector J12 lets you monitor signals between the FPGA and the FMC expansion connector 1 Table 1 8 defines the pin assignments Table 1 7 PS 2 Pin Assignments FPGA Pin Descript...

Page 22: ...6 V5 FMC_LA31_N A27 NC GND B1 NC GND B2 M8 FMC_LA08_P B3 M7 FMC_LA08_N B4 NC GND B5 K3 FMC_LA18_P B6 K2 FMC_LA18_N B7 NC GND B8 K5 FMC_LA10_P B9 K4 FMC_LA10_N B10 NC GND B11 P4 FMC_LA00_P_CC B12 P3 FMC_LA00_N_CC B13 NC GND B14 R8 FMC_LA30_P B15 R7 FMC_LA30_N B16 NC GND B17 K6 FMC_LA24_P B18 L7 FMC_LA24_N B19 NC GND B20 V1 FMC_LA19_P Table 1 8 Soft Touch Connector Pin Assignments Cont d Soft Touch ...

Page 23: ...ide the appropriate voltage to the FPGA bank used to communicate with the FMC module Be sure that the FMC adjustable power supply is configured for the voltage specified by the FMC module See FMC expansion connector for instructions about how to configure the adjustable power supplies B21 V2 FMC_LA19_N B22 NC GND B23 R5 FMC_LA29_P B24 R6 FMC_LA29_N B25 NC GND B26 T10 FMC_LA33_P B27 T9 FMC_LA33_N T...

Page 24: ... C26 T5 0_LA27_P D26 N1 0_LA26_P C27 U4 0_LA27_N D27 N2 0_LA26_N C28 NC GND D28 NC GND C29 NC GND D29 A25 TCK C30 AF23 1 SCL D30 E23 TDI C31 AE25 1 SDA D31 NC TDO C32 NC GND D32 NC 3P3VAUX C33 NC GND D33 D4 TMS C34 NC GA0 ground D34 NC TRSTL C35 NC 12P0V D35 NC GA1 GND C36 NC GND D36 NC 3P3V C37 NC 12P0V D37 NC GND C38 NC GND D38 NC 3P3V C39 NC 3P3V D39 NC GND C40 NC GND D40 NC 3P3V 1 I2C bus conn...

Page 25: ...4_P G11 NC GND H11 B1 0_LA04_N G12 M8 0_LA08_P H12 NC GND G13 M7 0_LA08_N H13 E1 0_LA07_P G14 NC GND H14 F2 0_LA07_N G15 J7 0_LA12_P H15 NC GND G16 H6 0_LA12_N H16 J8 0_LA11_P G17 NC GND H17 J9 0_LA11_N G18 K9 0_LA16_P H18 NC GND G19 K8 0_LA16_N H19 G3 0_LA15_P G20 NC GND H20 F3 0_LA15_N G21 M4 0_LA20_P H21 NC GND G22 M3 0_LA20_N H22 V1 0_LA19_P G23 NC GND H23 V2 0_LA19_N G24 G6 0_LA22_P H24 NC GN...

Page 26: ... FPGA and are used for the VCCIO of the FPGA banks connected to the FMC expansion connectors When no FMC expansion module is present the output voltage of PS1 should be set to 3 3V with the I2C bus interface to configure the digital potentiometer U23 See I2C Bus Addressing for detailed information Figure 1 3 illustrates the power supply architecture and maximum current handling by each supply The ...

Page 27: ...ors for instructions about how to properly configure the adjustable power supplies X Ref Target Figure 1 3 Figure 1 3 Spartan 3A DSP 3400A Edition Board Power Supply LTM4601 12 A switching regulator LT3872 2 A switching regulator To FMC expansion connectors 12V To FPGA I O 3 3V LTM4601 12 A switching regulator To Ethernet and FPGA I O EXP 2 5V LTM4601 12 A switching regulator To DDR2 XCF32P flash ...

Page 28: ..._N D11 C21 1_LA05_P C12 NC GND D12 B21 1_LA05_N C13 NC GND D13 NC GND C14 D17 1_LA10_P D14 B7 1_LA09_P C15 C16 1_LA10_N D15 C7 1_LA09_N C16 NC GND D16 NC GND C17 NC GND D17 E14 1_LA13_P C18 C5 1_LA14_P D18 F14 1_LA13_N C19 D6 1_LA14_N D19 NC GND C20 NC GND D20 F13 1_LA17_P_CC C21 NC GND D21 G13 1_LA17_N_CC C22 B19 1_LA18_P D22 NC GND C23 A19 1_LA18_N D23 B15 1_LA23_P C24 NC GND D24 A15 1_LA23_N C2...

Page 29: ...C GND H5 C13 1_CLK0_M2C_N G6 B14 1_LA00_P_CC H6 NC GND G7 A14 1_LA00_N_CC H7 D23 1_LA02_P G8 NC GND H8 C23 1_LA02_N G9 B23 1_LA03_P H9 NC GND G10 A22 1_LA03_N H10 D20 1_LA04_P G11 NC GND H11 C20 1_LA04_N G12 E21 1_LA08_P H12 NC GND G13 D21 1_LA08_N H13 C17 1_LA07_P G14 NC GND H14 B17 1_LA07_N G15 C10 1_LA12_P H15 NC GND G16 D10 1_LA12_N H16 D18 1_LA11_P G17 NC GND H17 C18 1_LA11_N G18 G12 1_LA16_P...

Page 30: ...1_LA21_P G26 NC GND H26 C15 1_LA21_N G27 A8 1_LA25_P H27 NC GND G28 B8 1_LA25_N H28 H17 1_LA24_P G29 NC GND H29 G17 1_LA24_N G30 J12 1_LA29_P H30 NC GND G31 K12 1_LA29_N H31 J16 1_LA28_P G32 NC GND H32 K16 1_LA28_N G33 C8 1_LA31_P H33 NC GND G34 D8 1_LA31_N H34 J11 1_LA30_P G35 NC GND H35 K11 1_LA30_N G36 B6 1_LA33_P H36 NC GND G37 C6 1_LA33_N H37 A4 1_LA32_P G38 NC GND H38 B4 1_LA32_N G39 NC VADJ...

Page 31: ... FPGA 22 I2C Fan Controller and Temperature voltage Monitor Onboard temperature and voltage monitoring and control are handled by an Analog Devices ADT7476A device This device is controlled through I2C I2C Bus Addressing and do the following Measure the voltage of the 5 V 3 3 V 1 8 V and 1 0 V supplies Measure the FPGA temperature through the DXP DXN pins on the FPGA Measure ambient temperature Re...

Page 32: ... The board supports configuration in several modes JTAG master serial slave serial master SelectMAP slave SelectMAP byte wide peripheral interface BPI up BPI down and SPI modes See Chapter 2 Configuration Options The FPGA is also equipped with four I O banks Table 1 17 defines the I O voltage applied to each bank 25 JTAG Header The JTAG header P5 allows programming devices and troubleshooting the ...

Page 33: ...elow Turning the potentiometer located below the LCD with a screwdriver allows you to adjust the image contrast of the LCD The LCD is equipped with a backlight that can be turned off by removing jumper JP10 27 User defined Buttons The functions of the five user defined buttons are determined by the designer all the buttons are directly connected to the FPGA Table 1 18 FPGA LCD Interface Signal FPG...

Page 34: ... 21 defines how to use the configuration jumpers Table 1 20 Serial Port FPGA Pin Assignments DB9 Pin FPGA Pin Description 2 V14 TX 3 AA20 RX Table 1 21 Configuration Jumpers Jumper Function On Off JP1 Prevents the USB controller from running the firmware in the I2C EEPROM 1 2 Does not run the firmware from I2C EEPROM Runs the firmware from the I2C EEPROM default JP2 Ethernet modes 1 2 GMII default...

Page 35: ...IP Switch FPGA Pin Assignments Switch No FPGA Pin Description 1 R26 FPGA_DIP_SW0 2 R25 FPGA_DIP_SW1 3 T23 FPGA_DIP_SW2 4 R24 FPGA_DIP_SW3 5 T18 FPGA_DIP_SW4 6 R22 FPGA_DIP_SW5 7 R21 FPGA_DIP_SW6 8 R20 FPGA_DIP_SW7 Table 1 23 User defined LED FPGA Pin Assignments LED No FPGA Pin Description 1 DS10 W23 GPIO_LED_0 2 DS11 V22 GPIO_LED_1 3 DS12 V25 GPIO_LED_2 4 DS13 V24 GPIO_LED_3 5 DS14 V23 GPIO_LED_4...

Page 36: ...ble 1 25 0 1 3 Config Mode 0 see Table 1 25 0 1 2 Board flash memory fallback 0 Disabled 1 Enabled 1 System ACE configuration When the System ACE configuration is enabled the System ACE controller on the bottom of the board configures the FPGA from the CompactFlash card reader on the bottom of the board whenever a CompactFlash card is inserted in the reader or the Reset ACE button is depressed 0 D...

Page 37: ...ors Microphone line in line out and headphones connectors All connectors are stereo with the exception of the microphone connector SLAVE SELECTMAP CONFIG FROM XCF32P FLASH 1 1 0 SLAVE SERIAL CONFIG FROM XCF32P FLASH 1 1 1 Table 1 26 Status LED Signals LED Signal Description DS6 DONE Status of the FPGA DONE signal DS7 INIT Status of the FPGA INIT signal DS8 EXTRA_LED_2 Not used DS9 EXTRA_LED_1 Not ...

Page 38: ...gistered 512 MB DDR2 SDRAM The DDR2 SDRAM is usually a Micron MT8HTF6464HY 53E or similar Serial presence detection SPD through an I2C interface to the memory is also supported by the FPGA See DDR2 memory for details Table 1 28 identifies the FPGA pin assignments used for the DDR2 interface Notes Only half the available memory of the DDR2 SDRAM that is 256 MB is available because of certain limita...

Page 39: ...DQ_11 AC23 DDR2_A_12 N17 DDR2_0_DQ_12 V19 DDR2_A_13 N20 DDR2_0_DQ_13 V21 DDR2_0_BA_0 M23 DDR2_0_DQ_14 AA23 DDR2_0_BA_1 M21 DDR2_0_DQ_15 AC26 DDR2_0_BA_2 G24 DDR2_0_DQ_16 U20 DDR2_0_CAS_B G23 DDR2_0_DQ_17 U18 DDR2_0_CK0_N K22 DDR2_0_DQ_18 U19 DDR2_0_CK0_P M19 DDR2_0_DQ_19 D26 DDR2_0_CK1_N F24 DDR2_0_DQ_20 E26 DDR2_0_CK1_P K23 DDR2_0_DQ_21 P25 DDR2_0_DM_0 K21 DDR2_0_DQ_22 N18 DDR2_0_DM_1 L22 DDR2_0_...

Page 40: ...em ACE controller is enabled with the configuration DIP switches The board also features a System ACE failsafe mode Under this mode if the System ACE controller detects a failed configuration attempt it automatically restarts under a predefined configuration image The failsafe mode is enabled by inserting two jumpers across JP7 and JP8 horizontally or vertically Caution Exercise caution when handl...

Page 41: ...o address 0x01 for FMC connector 2 To write to the volatile section of the digital pot make sure that address 0x08 is set to 0x80 Use the following steps to configure the digital pot to the appropriate voltages Vout 1 5V 1 Configure register 0x8 to value 0x80 2 Configure register 0x0 FMC 1 or 0x1 FMC 2 to value 0x8A Vout 1 8V 1 Configure register 0x8 to value 0x80 2 Configure register 0x0 FMC 1 or...

Page 42: ...544APW is used to separate those devices from one to the other Table 1 29 defines the various slave addresses accessible by the FPGA through the I2C MUX output Note To change the I2C MUX output you need to perform a write access to the I2C MUX slave address 0xE4 with the following data 0x04 for MUX 0 0x05 for MUX 1 0x06 for MUX 2 and 0x07 for MUX3 See the I2C MUX data sheet for detailed informatio...

Page 43: ...x62 0 1 1 0 0 0 1 R W DVI Monitor E DDC CI 0x6E 0 1 1 0 1 1 1 R W DVI Monitor E DDC 0xA0 1 0 1 0 0 0 0 R W DVI Monitor DDC Display Dependent Devices 0xFX 1 1 1 1 X X X R W Video Encoder 0xEC 1 1 1 0 1 1 0 R W I2C MUX 0xE4 1 1 1 0 0 1 0 R W Table 1 29 I2C Slave Device Addresses Cont d I2C MUX Device Slave Address A7 A6 A5 A4 A3 A2 A1 A0 Downloaded from Elcodis com electronic components distributor ...

Page 44: ...44 www xilinx com Spartan 3A DSP 3400A Edition User Guide UG498 v2 2 November 17 2008 Chapter 1 Introduction R Downloaded from Elcodis com electronic components distributor ...

Page 45: ...e board flash memory the FPGA the CPLD the FMC expansion connector The chain bypasses the FMC expansion connector if no expansion module is present Jumper JP4 must not be populated for appropriate JTAG operation The JTAG chain can be used to program the FPGA and to access the FPGA for hardware and software troubleshooting The JTAG header s connection to the JTAG chain allows a host computer to tra...

Page 46: ...n The board flash memory can also be used to program the FPGA This memory can hold up to two configuration images or up to four with compression selectable with the two least significant bits of the configuration address DIP switches See Spartan 3A DSP 3400A Edition Board Hardware page 16 for information The board is designed so the board flash memory can download bitstreams under master serial sl...

Page 47: ...chip to its factory default settings using the following equipment Xilinx download cable JTAG flying wires Downloading to the Spartan 3A DSP 3400A Edition Board 1 Connect a Xilinx download cable to the board using flying leads connected to jumper P2 2 From the Windows Start menu choose iMPACT to open the main iMPACT window 3 Click Boundary Scan then right click Add Xilinx Device 4 Locate the SVF f...

Page 48: ...ct Execute XSVF SVF 6 To finish programming the chip cycle the power by turning off the board power switch 7 After turning the board back on verify that the clock frequencies are correct X Ref Target Figure 3 2 Figure 3 2 Programming the IDT5V9885 on the Spartan 3A DSP 3400A Edition Board Using iMPACT Downloaded from Elcodis com electronic components distributor ...

Page 49: ...ating temperature range 0ºC to 70ºC non condensing Storage temperature range 55ºC to 150ºC non condensing Maximum Power Consumption The maximum power consumption is 6 84 W The power consumption specifications were calculated with a production test bitstream The power consumptions outlined above can vary according to the FPGA load FPGA Model Xilinx Spartan 3A DSP XC3SD3400A 4FGG676C DSP Performance...

Page 50: ...50 www xilinx com XtremeDSP Spartan 3A DSP User Guide UG489 v2 2 November 17 2008 R Downloaded from Elcodis com electronic components distributor ...

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