Xilinx Vivado MIPI CSI-2 Page 84 Product Manual Download

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MIPI CSI-2 RX Subsystem v4.0

PG232 July 02, 2019

www.xilinx.com

Appendix B:

Debugging

- Verify MIPI CSI-2 RX Controller interrupt status register to see if any ECC errors

getting reported. If there is frequent ECC 2-bit error getting reported means

some of the packets are not getting processed by MIPI CSI-2 RX Controller.

• Packets received by MIPI CSI-2 Subsystem with PPI Level Errors (like SoT Error, SoT sync

Error) and/or Controller level errors (like ECC 1-bit, ECC 2-bit, CRC).

Possible causes:
- Lane position mismatch between source (sensor) and MIPI CSI-2 RX Subsystem.
- Noise detected by MIPI DPHY as a valid packet

Debug instructions:
- Verify Lane positions of source (sensor) and MIPI CSI-2 RX Subsystem are

matching. Lane0 holds first byte of the packet, Lane1 holds the next byte and so

on.

- When HS_SETTLE parameter of MIPI DPHY is not sufficient enough during LP to

HS transition, MIPI DPHY may detect noise as a valid packet and when

subsequently processed by MIPI CSI-2 RX Controller reports these packets are

erroneous packets. Increase HS_SETTLE value either through MIPI DPHY registers

or through C_HS_SETTLE_NS parameter(hidden) available in MIPI CSI-2 RX

Subsystem.

For more debug information on MIPI DPHY, refer the

MIPI D-PHY LogiCORE IP Product Guide

(

PG202

)

[Ref 3]

. To debug further, capture the PPI signals using the Vivado® Logic analyzer

and confirm the bytes received through source (sensor) are as expected for short and long

packets.

Interface Debug

AXI4-Lite Interfaces

Read from a register that does not have all 0s as a default to verify that the interface is

functional. See

Figure B-1

for a read timing diagram. Output

s_axi_arready

asserts when

the read address is valid, and output

s_axi_rvalid

asserts when the read data/response

is valid. If the interface is unresponsive, ensure that the following conditions are met:

• The

lite_aclk

inputs are connected and toggling.

• The interface is not being held in reset, and

lite_aresetn

is an active-Low reset.

• The main subsystem clocks are toggling and that the enables are also asserted.
• If the simulation has been run, verify in simulation and/or a debug feature capture that

the waveform is correct for accessing the AXI4-Lite interface.

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Summary of Contents for Vivado MIPI CSI-2

Page 1: ...MIPI CSI 2 Receiver Subsystem v4 0 Product Guide Vivado Design Suite PG232 July 02 2019...

Page 2: ...17 Port Descriptions 17 Register Space 21 Chapter 3 Designing with the Subsystem General Design Guidelines 37 Shared Logic 37 I O Planning 42 Clocking 44 Resets 47 Protocol Description 48 Chapter 4 De...

Page 3: ...rdware Validation 78 Appendix B Debugging Finding Help on Xilinx com 81 Debug Tools 82 Hardware Debug 83 Interface Debug 84 Appendix C Additional Resources and Legal Notices Xilinx Resources 87 Docume...

Page 4: ...ive lanes within the configured lanes during subsystem generation Interrupt generation to indicate subsystem status information Internal D PHY allows direct connection to image sources Support for MIP...

Page 5: ...ect the required hardware blocks needed to build the subsystem Figure 1 1 shows the subsystem architecture The subsystem consists of the following sub cores MIPI D PHY MIPI CSI 2 RX Controller AXI Cro...

Page 6: ...native MIPI IOB support You will have to target either HR bank I O or HP bank I O for the MIPI IP implementation For more information on MIPI IOB compliant solution and guidance refer D PHY Solutions...

Page 7: ...packet header CRC check for payload data Long packet ECC CRC forwarding capability for downstream IPs Maximum data rate of 2 5 Gb s Pixel byte packing based on data format AXI4 Lite interface to acces...

Page 8: ...r to downstream IPs This allows to re calculate ECC CRC by the downstream IPs in certain functional safety applications See Port Descriptions for details on signal mapping In error scenarios like abru...

Page 9: ...ort one main data type from the Vivado IDE for pixel data and a User Defined Byte based Data type for metadata When multiple data types are transferred for example RAW10 and User Defined Byte based Da...

Page 10: ...of the video_out interface is 24 bits Within the 24 bits the RAW8 pixels are aligned to the most significant bits as shown in the following table IMPORTANT In a multi pixel scenario pixel width varies...

Page 11: ...own in the following table Table 1 3 Pixel Packing for RAW8 and RAW6 Data Types Bit Positions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RAW8 q7 q6 q5 q4 q3 q2 q1 q0 p7 p6 p5 p4 p3 p2 p1 p0 RAW6 q5 q4 q3 q...

Page 12: ...obile platforms such as mobile phones and tablets However the large volumes and the economies of scale of the mobile industry is forcing other applications to also adopt these standards As such MIPI b...

Page 13: ...by the following tools Vivado synthesis Vivado implementation write_bitstream Tcl command IMPORTANT IP license level is ignored at checkpoints The test confirms a valid license exists It does not che...

Page 14: ...l Interface see the AXI4 Stream Video IP and System Design Guide UG934 Ref 2 Performance This section details the performance information for various core configurations Latency The CSI2 RX Subsystem...

Page 15: ...tions X Ref Target Figure 2 1 Figure 2 1 MIPI CSI2 RX Subsystem Latency Calculation Table 2 1 D PHY Latency Data Type Pixel Mode Line Rate Latency in rxbyteclk HS_SETTLE internal latency RAW20 Single...

Page 16: ...numbers for various core configurations Table 2 2 MIPI CSI2 RX Controller latency Data Type Pixel Mode Line Rate Latency in rxbyteclk Latency in Video Clock RAW20 Single 1000 25 60 RAW8 Single 1000 2...

Page 17: ...Single 1000 48 RAW8 Dual 1000 48 RAW8 Quad 1000 48 RAW10 Single 1000 53 RAW10 Dual 1200 59 RAW10 Quad 800 47 Notes 1 All the calculations are made for a single lane design with a fixed video clock of...

Page 18: ...ed on Data type and number of pixels selected in the Vivado IDE see video_out Port Width video_out_tdest 9 0 Output 9 4 Data Type 3 0 Virtual Channel Identifier VC AXI4 Stream Interface when Embedded...

Page 19: ...width selected in the Vivado IDE 9 4 Data type 3 0 Virtual Channel Identifier VC video_out_tkeep n 8 1 0 Output Specifies valid bytes video_out_tlast Output End of line video_out_tready Input Slave re...

Page 20: ...yte group x indicates byte group 0 1 2 3 y indicates bitslice0 position 0 for the lower nibble 6 for the upper nibble RTL Design There is no need to drive any data on these ports IP Integrator These p...

Page 21: ...r within the MIPI CSI 2 RX controller core Table 2 6 Sub Core Address Offsets IP Cores Offset MIPI CSI 2 RX Controller 0x0_0000 AXI IIC 0x1_0000 MIPI D PHY 0x2_0000 1 Notes 1 When the AXI IIC core is...

Page 22: ...information 2 of the current processing packet with VC of 0 0x68 Image Information 1 for VC1 Image information 1 of the current processing packet with VC of 1 0x6C Image Information 2 for VC1 Image i...

Page 23: ...ation 1 for VC10 Image information 1 of the current processing packet with VC of 10 0xB4 Image Information 2 for VC10 Image information 2 of the current processing packet with VC of 10 0xB8 Image Info...

Page 24: ...akes core out of soft reset All registers reset to their default value except for this bit Core Enable and Active lanes configuration In addition to resetting registers when this bit is set to 1 Shut...

Page 25: ...Lanes cannot exceed the number of lanes as set by the Serial Data Lanes parameter at generation time 2 A read from this register reflects the current number of lanes being used by core This is useful...

Page 26: ...rresponding Interrupt Enable register IER bits are used to generate interrupts 0 Disabled Interrupt generation blocked irrespective of IER bits Table 2 12 Interrupt Status Register 0x24 Bits Name Rese...

Page 27: ...ors detected in the received packet header 10 ECC 1 bit error Detected and Corrected ErrEccCorrected 0x0 R W1C Asserted when an ECC syndrome was computed and a single bit error in the packet header wa...

Page 28: ...ured in the ISR take a few clock periods to reflect in the register clock domain from the PPI clock domain due to CDC blocks 7 Frame level errors due to ErrSotSyncHS are mapped to the recent VC proces...

Page 29: ...ent packet being processed has Start of Transmission Synchronization Error reported through PPI interface Reset Sequence Write 1 to clear this bit Priority Set condition takes priority over reset sequ...

Page 30: ...The core waits for the next packet to process Table 2 22 Frame Synchronization Error Set Condition s Set by the core when a Frame End FE is not paired with a Frame Start FS on the same virtual channel...

Page 31: ...re enabling disabling in this register see the ISR descriptions in Table 2 12 30 23 Reserved N A N A 22 Word Count WC corruption 0x0 R W 21 Incorrect lane configuration 0x0 R W 20 Short packet FIFO fu...

Page 32: ...eneric short packet code Table 2 27 VCX Frame Error 0x34 Bits Name Access Default Value Description 31 24 Reserved N A N A Reserved 23 Frame synchronization error for VC15 R W1C 0x0 Asserted when an F...

Page 33: ...W1C 0x0 Asserted when an FE is not paired with a Frame Start FS on the same virtual channel 10 Frame level error for VC9 R W1C 0x0 Asserted after an FE when the data payload received between FS and FE...

Page 34: ...en FS and FE contains errors The data payload errors are CRC errors 1 Frame synchronization error for VC4 R W1C 0x0 Asserted when an FE is not paired with a Frame Start FS on the same virtual channel...

Page 35: ...Vivado IDE For details about AXI IIC registers see the AXI IIC Bus Interface v2 0 LogiCORE IP Product Guide PG090 Ref 5 1 SoT error 0x0 R Detection of SoT Error ErrSotHS Indicates SoT error detected 0...

Page 36: ...com Chapter 2 Product Specification MIPI D PHY Registers The MIPI D PHY registers are available when D PHY Register Interface is selected in Vivado IDE For details about MIPI D PHY registers see the M...

Page 37: ...the image sensor The Protocol Configuration Register 1 0 can be used to dynamically configure the active lanes used by the subsystem using the following guidelines 1 Program the required lanes in the...

Page 38: ...er contained in the subsystem or in the example design In these figures component_name is the name of the generated subsystem The difference between the two hierarchies is the boundary of the subsyste...

Page 39: ...e design if This is not the first MIPI CSI 2 RX Subsystem instance in a multi subsystem design that shares PLLs generated from other MIPI CSI 2 RX Subsystem that is configured with shared logic in the...

Page 40: ...the same line rate when sharing clkoutphy within IO bank There must be at least one core with master mode in a system whose clocks can be shared with slave mode cores IMPORTANT Initialize all MIPI in...

Page 41: ...clocking resources in such scenario MIPI CSI 2 TX Subsystem need to be configured using Include Shared Logic in Core option under Shared Logic tab IMPORTANT The master and slave can be configured wit...

Page 42: ...f the I O The propagation of strobes to the RX data pins follows the inter byte and inter nibble clocking rules given in the UltraScale Architecture SelectIO Resources User Guide UG571 Ref 16 All lane...

Page 43: ...single HP IO bank depends on the number of clock capable pins available on that bank For example HP IO Bank 67 on ZCU102 UltraScale device has eight clock capable pins as shown below which allows eig...

Page 44: ...tem video_aclk 2 Clock used as core clock for all IP cores in the subsystem dphy_clk_200M See the MIPI D PHY LogiCORE IP Product Guide PG202 Ref 3 for information on this clock clkoutphy_out The clkou...

Page 45: ...eclkhs 1000 8 125 MHz Core clock Core clock for the modules Lanes 4 of rxbyteclkhs Example 1 Line rate 1000 Mb s Lanes 4 Core clock 125 4 4 125 MHz Example 2 Lane rate 1000 Mb s Lanes 3 Core clock 125...

Page 46: ...ement block is written is 87 5 MHz 3 Because the lane management block read path operates on a 32 bit 4 byte data path the minimum required video clock is 87 5 MHz 3 4 or higher For a MIPI interface w...

Page 47: ...reset ports lite_aresetn Active Low reset for the AXI4 Lite register interface video_aresetn Active Low reset for the subsystem blocks The duration of video_aresetn should be a minimum of 40 dphy_clk...

Page 48: ...hows an example based on a subsystem base address of 0x44A0_0000 32 bits when the AXI IIC core is included and the MIPI D PHY register interface is enabled AXI IIC IP Core Programming See the AXI IIC...

Page 49: ...nterrupts Re enable the core set the Core Enable bit to 1 or the Soft Reset bit to 0 Active Lanes Configuration The Protocol Configuration Register 1 0 can be used to dynamically configure the active...

Page 50: ...ng in stop state After updating the active lanes field if the MIPI DPHY RX Clock lane is in stop state you can continue without waiting for the Active Lane bit field getting updated Once the DPHY RX C...

Page 51: ...mizing and generating the subsystem in the Vivado IP integrator see the Vivado Design Suite User Guide Designing IP Subsystems using IP Integrator UG994 Ref 8 for detailed information IP integrator mi...

Page 52: ...its original name Names must begin with a letter and must be composed from the following characters a through z 0 through 9 and _ The default is mipi_csi2_rx_subsystem_0 Board Tab The Board tab page...

Page 53: ...HPC0 connector selected as LI IMX274MIPI FMC V1 0 during board selection for 4 lane MIPI CSI 2 Rx Subsystem This selection automatically configures the MIPI CSI 2 Rx Subsystem to support IMX274 camera...

Page 54: ...to enable the register interface for the MIPI D PHY core Enable Deskew Detection Select to enable Deskew sequence detection and centre alignment of clock and data lanes in MIPI D PHY Note Applicable o...

Page 55: ...ffer Depth Depth of internal RAM used to accommodate throttling on the output video interface Values are 128 256 512 1024 2048 4096 8192 or 16384 Note There is no throttling allowed on the input to th...

Page 56: ...Design Flow Steps Shared Logic Select whether the PLL are included in the core or in the example design Values are Include Shared Logic in core Include Shared Logic in example design X Ref Target Figu...

Page 57: ...I O bank for clock lane and data lane implementation Clock Lane Select the LOC for clock lane This selection determines the I O byte group within the selected HP I O bank Data Lane 0 1 2 3 Displays th...

Page 58: ...l to connect MIPI Camera Sensor and MIPI Display Supported value s are LI IMX274MIPI FMC V1 0 Single Sensor Design Topology Application example design configuration type Select MIPI_Video_Pipe_Camera_...

Page 59: ...ation Mode C_CAL_MODE None IDELAY Tap Value C_IDLY_TAP 1 Include IDELAYCTRL in Core C_SHARE_IDLYCTRL False Enable 300 MHZ Clock for IDELAYCTRL C_EN_CLK300M False Embedded non image Interface CSI_EMB_N...

Page 60: ...Guide UG571 Ref 16 See the respective Xilinx 7 series FPGA family device data sheet for details on the upper line rate limits Clock Frequencies See Clocking Clock Management The MIPI CSI 2 RX Subsyst...

Page 61: ...UltraScale family The LOC and I O standards must be specified in the XDC file for all input and output ports of the design The MIPI CSI 2 RX Subsystem MIPI D PHY sub core generates the I O pin LOC for...

Page 62: ...ystem MIPI CSI 2 RX Subsystem provides an Application Example Design which can be implemented on the hardware See Chapter 5 Application Example Design for details For comprehensive information about V...

Page 63: ...Scale ZCU102 board On the capture path the system receives images captured by IMX274 image sensor Processed images are displayed on either the HDMI monitor or MIPI DSI Display A block diagram of the M...

Page 64: ...HDMI TX Subsystem to be displayed The HDMI TX Subsystem is available as an alternative if a MIPI DSI compliant display panel is not available Using the GPIO IP one of the destination video paths is s...

Page 65: ...power supply JTAG USB Platform cable or USB cable Type A to micro B USB cable Type A to micro B for USB UART HDMI cable HDMI Monitor supporting 4K 30 fps with at least 12 bpc color depth AUOS DSI Dis...

Page 66: ...DMI cable to the ZCU102 HDMI port top port Figure 5 4 c Connect the other end of the HDMI cable to the HDMI monitor d Switch on the HDMI monitor and select HDMI as input source e Connect USB UART type...

Page 67: ...port of board g Ensure the board switches and jumpers are in position as shown in Figure 5 5 Ensure that all SW6 switches are set to the ON position to allow programming from JTAG h Connect the USB U...

Page 68: ...y 02 2019 www xilinx com Chapter 5 Application Example Design 5 Start a Hyper Terminal program on the host PC with the following settings Baud rate 115200 Data Bits 8 Parity None X Ref Target Figure 5...

Page 69: ...SDB prompt to program FPGA and to execute the application xsdb source xsdb tcl 6 To observe the results start a Hyper Terminal program on the host PC and configure its serial port Interface 0 to 11520...

Page 70: ...ration section displayed on the console Implementing the Example Design 1 Open the Vivado Design Suite The Vivado IDE Getting Started page contains links to open or create projects and to view documen...

Page 71: ...ge click Next 6 In the Add Existing IP optional dialog box click Next 7 In the Add Constraints optional dialog box click Next 8 In the Default Part dialog box click Boards to specify the board for the...

Page 72: ...lication Example Design 9 Review the New Project Summary page Verify that the data appears as expected per the steps above and click Finish X Ref Target Figure 5 8 Figure 5 8 Vivado IDE Default Part X...

Page 73: ...nder Video Connectivity then double click on it For the Application Example Design flow IP configuration is based on options selected in Application Example Design tab You can rename the IP component...

Page 74: ...com Chapter 5 Application Example Design The Generate Output Products dialog box appears Click Generate You may optionally click Skip if you want to skip generating the output products X Ref Target F...

Page 75: ...he MIPI CSI 2 Rx Subsystem component under Design source and click Open IP Example Design Note As this step involves the generation of complete system involving multiple subsystems it would take some...

Page 76: ...generated You may proceed to Run Synthesis Implementation and Generate Bitstream to validate the design on board or use the IPI system as a reference for camera capture to video display path Click Gen...

Page 77: ...Design Known Issues Short duration of flickering appears while changing available options such as resolution change from the Application Menu Sometimes MIPI DSI Display goes blank when you switch from...

Page 78: ...ested in hardware for functionality performance and reliability using Xilinx evaluation platforms The MIPI CSI 2 RX Subsystem verification test suites for all possible modules are continuously being u...

Page 79: ...Sony IMX274 ZCU102 xczu9eg ffvb1156 2 e 1440Mb s 4 Lanes RAW10 RAW12 All supported modes by sensor Sony IMX224 ZCU102 xczu9eg ffvb1156 2 e 149Mb s 594Mb s 1 2 4 Lanes RAW10 RAW12 All pixel QVGA and W...

Page 80: ...hieving higher line rates For PCB guidelines refer to UltraScale Architecture PCB Design User Guide UG583 Ref 17 Table A 4 Loopback Testing with Xilinx 7 Series FPGA Devices Board Device Line Rate Lan...

Page 81: ...urther product support Documentation This product guide is the main document associated with the MIPI CSI 2 Receiver Subsystem This guide along with documentation related to all products that aid in t...

Page 82: ...mize the solution beyond that allowed in the product documentation Change any section of the design labeled DO NOT MODIFY To contact Xilinx Technical Support navigate to the Xilinx Support web page De...

Page 83: ...er than the output data rate Consider either decreasing input data rate DPHY Line rate or increase output data rate Select appropriate output pixel per Clock Single Dual Quad Ensure that the PULLUP co...

Page 84: ...kets are erroneous packets Increase HS_SETTLE value either through MIPI DPHY registers or through C_HS_SETTLE_NS parameter hidden available in MIPI CSI 2 RX Subsystem For more debug information on MIP...

Page 85: ...uration Ensure Stream line buffer full condition not getting reported in subsystem Interrupt Status register Sideband Information on AXI4 Stream Interfaces Sideband information such as frame and line...

Page 86: ...MIPI CSI 2 RX Subsystem v4 0 86 PG232 July 02 2019 www xilinx com Appendix B Debugging Figure B 1 Sideband Information TUSER Timing Diagram Send Feedback...

Page 87: ...cumentation Navigator DocNav From the Vivado IDE select Help Documentation and Tutorials On Windows select Start All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx...

Page 88: ...mipi org specifications physical layer D PHY Specification 7 Vivado Design Suite AXI Reference Guide UG1037 8 Vivado Design Suite User Guide Designing IP Subsystems using IP Integrator UG994 9 Vivado...

Page 89: ...Updated examples in the Pixel Packing for Multiple Data Types section to match the alignment described in AXI4 Stream Video IP and System Design Guide UG934 04 04 2018 3 0 ECC and CRC of long packets...

Page 90: ...ials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of Sale which can be viewed at https www xilinx...

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