MIPI CSI-2 RX Subsystem v4.0
46
PG232 July 02, 2019
Chapter 3:
Designing with the Subsystem
The read path of the lane management block in the CSI-2 RX Controller operates on a 32-bit
data path (irrespective of the number of lanes) and uses the video clock for processing the
data. Therefore, the minimum required video clock should be greater than or equal to the
effective PPI clock divided by 4.
The following examples illustrate this:
• For a MIPI interface with 1000 Mb/s per lane, 1 lane design, the effective rate at which
the lane management block is written is 125 MHz. Because the lane management block
read path operates on a 32-bit (4-byte) data path, the minimum required video clock is
125 MHz / 4 or higher.
• For a MIPI interface with 800 Mb/s, 2 lane design, the effective rate at which the lane
management block is written is 100 MHz * 2. Because the lane management block read
path operates on a 32
–
bit (4-byte) data path, the minimum required video clock is
(100 MHz * 2) / 4 or higher.
• For a MIPI interface with 700 Mb/s per lane, 3 lane design, the effective rate at which
the lane management block is written is 87.5 MHz * 3. Because the lane management
block read path operates on a 32-bit (4-byte) data path, the minimum required video
clock is (87.5 MHz * 3) / 4 or higher.
• For a MIPI interface with 1200 Mb/s per lane, 4 lane design, the effective rate at which
the lane management block is written is 150 MHz * 4. Because the lane management
block read path operates on 32-bit (4-byte) data path, the minimum required video
clock is (150 MHz * 4) / 4 or higher.
• Apart from the minimum video clock requirement mentioned above, it is equally
important to ensure that at any given time, the output bandwidth of the subsystem is
greater than or equal to the input bandwidth.
The following example illustrates this-
Video
clock
Clock used for
video interface
for single pixel video
clock=pixel clock
for dual pixel video
clock=pixel clock/2
for quad pixel video
clock=pixel clock/4
Example 1
125 MHz for single pixel wide
125 MHz/2 = 62.5 MHz for dual pixel
125 MHz/4 = 31.25 MHz for quad pixel
Example 2
93.75 MHz for single pixel wide
93.75 MHz/2 = 46.875 MHz for dual pixel
93.75 MHz/4 = 23.43 MHz for quad pixel
Notes:
1. This clock is not used in the system. It is only listed to illustrate the clock relations.
2. bbp is bits per pixel.
Table 3-2:
Clocking
(Cont’d)
Clock
Function
Frequency
Example
