360
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 3:
User Programming Model
R
Special-Purpose Registers (SPRs)
Most registers in the PPC405 are
special-purpose registers
, or SPRs. SPRs control the
operation of debug facilities, timers, interrupts, storage control attributes, and other
processor resources. All SPRs can be accessed explicitly using the
move to special-purpose
register
(
mtspr
) and
move from special-purpose register
(
mfspr
) instructions. See
for more information on these instructions. A few
registers are accessed as a by-product of executing certain instructions. For example, some
branch instructions access and update the link register.
The PPC405 SPRs in the user-programming model are shown in
. The SPR
number (SPRN) for each SPR is shown above the corresponding register. See
for a complete list of all SPRs (user and privileged)
supported by the PPC405.
Simplified instruction mnemonics are available for the
mtspr
and
mfspr
instructions for
some SPRs. See
for more information.
General-Purpose Registers (GPRs)
The PPC405 contains thirty-two 32-bit general-purpose registers (GPRs), numbered
r
0
through
r
. Data from memory are read into GPRs using load
instructions and the contents of GPRs are written to memory using store instructions. Most
integer instructions use the GPRs for source and destination operands.
Figure 3-1:
PPC405 User Registers
UG011_30_033101
USPRG0
User-SPR General-Purpose
Registers
(SPR 0x100)
SPR General-Purpose
Registers
(read only)
SPRG4
SPR 0x104
SPRG5
SPR 0x105
SPRG6
SPR 0x106
SPRG7
SPR 0x107
Time-Base Registers
(read only)
TBU
TBR 0x10C
TBL
TBR 0x10D
General-Purpose Registers
r
0
.
.
.
r
1
r
31
CR
Condition Register
CTR
Count Register
SPR 0x009
LR
Link Register
SPR 0x008
XER
Fixed-Point Exception Register
SPR 0x001
0
31
Figure 3-2:
General Purpose Registers (R0-R31)
