344
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 2:
Operational Concepts
R
User Mode
User mode
restricts access to some registers and instructions. The
user-programming model
comprises the register set and instruction set supported by the processor running in user
mode, and is a subset of the privileged-programming model. Operating systems typically
confine the execution of application programs to user mode, thereby protecting system
resources and other software from the effects of errant applications.
The registers available in user mode are shown in
. Refer to the
corresponding section in
for a description of each register. All instructions are
available in user mode except as shown in
User mode is sometimes referred to as
problem state
.
Memory Organization
PowerPC programs reference memory using an effective address computed by the
processor when executing a load, store, branch, or cache-control instruction, and when
fetching the next-sequential instruction. Depending on the address-relocation mode, this
effective address is either used to directly access physical memory or is treated as a virtual
address that is translated into physical memory.
Effective-Address Calculation
Programs reference memory using an
effective address
(also called a
logical address)
. An
effective address (EA) is the 32-bit unsigned sum computed by the processor when
accessing memory, executing a branch instruction, or fetching the next-sequential
instruction. An EA is often referred to as the
next-instruction address
(NIA) when it is used
to fetch an instruction (sequentially or as the result of a branch). The input values and
method used by the processor to calculate an EA depend on the instruction that is
executed.
When accessing data in memory, effective addresses are calculated in one of the following
ways:
•
EA = (
r
A|0)—this is referred to as
register-indirect
addressing.
•
EA = (
r
A|0) + offset—this is referred to as
register-indirect with immediate-index
addressing.
•
EA = (
r
A|0) + (
r
B)—this is referred to as
register-indirect with index
addressing.
Note:
In the above, the notation
(r
A|0) specifies the following:
If the
r
A instruction field is 0, the base address is 0.
If the
r
A instruction field is not 0, the contents of register
r
A are used as the base address.
When instructions execute sequentially, the next-instruction effective address is the
current-instruction address (CIA) + 4. This is because all instructions are four bytes long.
When branching to a new address, the next-instruction effective address is calculated in
one of the following ways:
•
NIA = CIA + displacement—this is referred to as
branch-to-relative
addressing.
•
NIA = displacement—this is referred to as
branch-to-absolute
addressing.
•
NIA = (LR)—this is referred to as
branch to link-register
addressing.
•
NIA = (CTR)—this is referred to as
branch to count-register
addressing.
When the NIA is calculated for a branch instruction, the two low-order bits (30:31) are
always cleared to 0, forcing word-alignment of the address. This is true even when the
address is contained in the LR or CR, and the register contents are not word-aligned.
All effective-address computations are performed by the processor using unsigned binary
arithmetic. Carries from bit 0 are ignored and the effective address wraps from the
maximum address (2
32
-1) to address 0 when the calculation overflows.
