Xilinx Virtex-II Pro PPC405, User Manual

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570 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 11: Instruction Set
R
Syntax —The assembler syntax used for the instruction. Some instructions have up to four
possible syntax variations. These variations depend on whether the instruction form
contains an overflow-enable bit (OE) and/or a record bit (Rc). For these instructions, the
use of the OE and Rc bits is reflected in the instruction mnemonic.
Form —The format used to encode the instruction. All PowerPC instructions are encoded
using one of the following forms: A, B, D, I, M, SC, X, XL, XO, XFX, or XFL. See
Instructions Grouped by Form , page 792 for a description of each form and a list of
instructions sorted by form.
Encoding —The specific encoding used to specify the instruction and its operands. See
Instruction Encoding , below for more information.
Description —A description of how each instruction operates on the specified operands.
The effect of the instruction on the CR and XER registers is also described. For some
instructions, additional information is provided as to the purpose and use of the
instruction. Many descriptions have cross-references to more detail in other sections of the
manual. If simplified mnemonics are defined for an instruction, a cross-reference into
Appendix C, Simplified Mnemonics is provided.
Pseudocode —A description of the instruction operation using a semi-formal language.
The pseudocode conventions are used throughout this document and are described in the
Preface in
Pseudocode Conventions , page 315 . The precedence of pseudocode operations
is further described in the Preface in Operator Precedence , page 317 .
Registers Altered —A summary of the PowerPC registers that are modified by executing
the instruction.
Exceptions —A list of the exceptions that can occur as a result of executing the instruction.
Asynchronous exceptions and exceptions associated with instruction fetching are not
listed because those exceptions can occur with any instruction. This section also describes
the effect of invalid instruction forms on instruction execution.
Compatibility —A brief description of instruction portability to other PowerPC
implementations.
Instruction Encoding
All instructions are four bytes long and are word aligned. Bits 0:5 always contain the
primary opcode, which is used to determine the instruction form. The instruction form
defines fields within the encoding for identifying the operands. Some instruction forms
define an extended opcode field for specifying additional instructions.
All instruction fields belong to one of the following categories:
• Defined
These instructions contain values, such as opcodes, that cannot be altered. The
instruction encoding diagrams specify the values of defined fields. If any bit in a
defined field does not contain the expected value, the instruction is illegal and an
illegal-instruction exception occurs.
• Variable
These fields contain operands, such as general-purpose register identifiers or
displacement values, that can vary from instruction to instruction. The instruction
encoding diagrams specify the operands in variable fields.
• Reserved
Bits in a reserved field should be cleared to 0. In the instruction encoding diagrams,
reserved fields are shaded and contain a value of 0. If any bit in a reserved field does
not contain 0, the instruction form is invalid and its result is undefined. Unless
otherwise noted, invalid instruction forms execute without causing an illegal-
instruction exception.