Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 459
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Cache Control
R
The dcbt and dcbtst instructions are implemented identically on the PPC405. On some
processor implementations, these instructions can cause separate bus operations to occur
that differentiate data-cache touches for loads from data-cache touches for stores.
dcbz establishes a cacheline without accessing system memory. It is possible for software
to erroneously use this instruction to establish a cacheline for unimplemented memory
locations. A subsequent access that attempts to update unimplemented system memory
(such as a cacheline replacement) can cause unpredictable results or system failure.
Core-Configuration Register
The core-configuration register (CCR0) is a 32-bit register used to configure memory-
system features, including:
• Whether cache misses cause cacheline allocation.
• Whether instruction prefetching is permitted.
• The size of non-cacheable requests over the processor local bus.
• The priority given by the processor when it makes a request over the processor local
bus on behalf of a cache unit.
• Enablement of the U0 storage-attribute exception.
• Cache-debug features.
Figure 5-13 shows the format of the CCR0. The fields in CCR0 are defined as shown in
Table 5-6 .
dcbz Data Cache Block Clear to Zero An effective address (EA) is calculated using
register-indirect with index addressing:
EA
=
( r A|0)
+
( r B)
If the byte referenced by EA is not cached, a
cacheline is allocated for that address. The
cacheline containing the byte referenced by EA is
cleared to 0 and marked modified (dirty).
If the EA is non-cacheable or write-through, an
alignment exception occurs. The alignment-
interrupt handler can emulate the operation by
clearing the corresponding bytes in system
memory to 0.
r A, r B
dccci Data Cache Congruence Class
Invalidate Invalidates both data-cache ways in the
congruence class specified by the effective address
(EA). Any modified data is lost.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r A, r B
dcread Data Cache Read If the byte specified by the effective address (EA) is
cached by the data cache,
r D is loaded with
information from one of the two ways indexed by
the EA. CCR0 fields specify the cache way and
whether the data tag or data word is loaded into
r D. See dcread Instruction , page 469 for more
information.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r D, r A, r B
Table 5-5: Data-Cache Control Instructions (Continued)
Mnemonic Name Operation
Operand
Syntax