Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 469
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Cache Debugging
R
Synchronization is required between the icread instruction and the mfspr that reads the
ICDBDR contents. This guarantees that the values read by mfspr are those loaded by the
most-recent execution of icread . The following assembler-code sequence provides an
example:
icread r
A,
r
B ! Read instruction-cache information.
isync ! Ensure icread completes execution.
mficdbdr r D ! Copy information to GPR.
dcread Instruction
The
dcread
instruction reads data cacheline information for a specific effective address. A
congruence class is selected from the data cache using the effective-address bits EA
19:26
. A
way is selected from the congruence class using the cache-way select field (CWS) in the
CCR0 register. CCR0[CWS]
=
0 selects way A and CCR0[CWS]
=
1 selects way B. The
cacheline information in the selected congruence-class and way is loaded into the
destination GPR,
r
D. Figure 5-15 shows the format of the cache information loaded into
r
D.
The information fields loaded in r D are defined as shown in Table 5-8 .
0 19 26 27 28 31
INFO D V LRU
Figure 5-16: Information Fields Loaded by dcread into rD
Table 5-9: dcread Information-Field Definitions
Bit Name Function Description
0:18 INFO Data-Cache Information
CCR0[CIS]
=
0—Data word.
CCR0[CIS]
=
1—Data tag.
Contains either the cacheline tag or a single data word from the
cacheline. If a data word is loaded, it is specified using effective-
address bits EA
27:29
. CCR0[CIS] controls the type of information
loaded into this field.
19:25 Reserved
26 D Dirty
0—Cacheline is not dirty.
1—Cacheline is dirty.
Contains a copy of the cacheline dirty bit, indicating whether the
line contains modified data.
27 V Valid
0—Cacheline is not valid.
1—Cacheline is valid.
Contains a copy of the cacheline valid bit.
28:30 Reserved
31 LRU Least-Recently Used
0—Way A is least-recently
used.
1—Way B is least-recently
used.
Contains the LRU bit for the congruence class associated with the
cacheline.