Xilinx Virtex-II Pro PPC405, User Manual

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426 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 3: User Programming Model
R
Semaphore Synchronization
Table 3-53 lists the PowerPC semaphore-synchronization instructions. These instructions are
used to implement common semaphore operations, including test and set, compare and
swap, exchange memory, and fetch and add. Examples of these semaphore operations are
found in
Synchronization Examples , page 837 .
The lwarx and stwcx. instructions are typically used by system programs and are called by
application programs as needed. Generally, a program uses lwarx to load a semaphore
from memory, causing a reservation to be set (the processor maintains the reservation
internally). The program can compute a result based on the semaphore value and
conditionally store the result back to the same memory location using the
stwcx.
instruction. The conditional store is performed based on the existence of the reservation
established by the preceding
lwarx instruction. If the reservation exists when the store is
executed, the store is performed and CR0[EQ] is set to 1. If the reservation does not exist
when the store is executed, the target memory location is not modified and CR0[EQ] is
cleared to 0.
Table 3-52: Synchronization Effects of PowerPC Instructions
Context Synchronizing Execution Synchronizing Storage Synchronizing
isync
rfci
2
rfi
2
sc
eieio
1
isync
mtmsr
2
rfci
2
rfi
2
sc
sync
eieio
sync
Notes:
1. As implemented on the PPC405.
2. Privileged instruction.
Table 3-53: Semaphore Synchronization Instructions
Mnemonic Name Operation
Operand
Syntax
lwarx Load Word and Reserve Indexed r D is loaded with the word in memory addressed
using register-indirect with index addressing:
EA
=
( r A|0)
+
( r B)
A reservation corresponding to the address is
maintained by the processor.
r D, r A, r B
stwcx. Store Word Conditional Indexed An effective address is computed using register-
indirect with index addressing:
EA
=
( r A|0)
+
( r B)
If a reservation exists, the contents of r S are stored
into the memory word specified by the effective
address, and the reservation is cleared. If a
reservation does not exist,
r S is not stored.
CR0[EQ] is set to 1 if the reservation exists,
otherwise it is cleared to 0.
r S, r A, r B