Xilinx Virtex-5 RocketIO GTP, User Manual

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166 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 7: GTP Receiver (RX)
R
data is received because the CDR is not locked, or the CDR is locked and the phase
alignment has not yet been attempted.
To work around this problem, RX phase alignment must be attempted several times and
the output data evaluated after each attempt. Good data is received if the phase is aligned
while the RX CDR is locked.
The flow diagram in Figure 7-23 shows the series of steps required for successful RX phase
alignment. Any number of clock cycles can be used for the CDR lock time, but using a
larger number decreases the number of cycles through the states.
Figure 7-23: Steps Required for Successful RX Phase Alignment
W ait for CDR to Lock
Final
RXPMASETPHASE
Assertion for Phase
Alignment w ith Kno w n
CDR Lock (32 Cycles)
Assert
RXPMASETPHASE
32 RXUSRCLK2
Cycles to
Phase Align
W ait for PLL Lock
and DCM/PLL Lock.
RX N /RXP Sho u ld Be
Dri v en
Fail
UG196_c7_34_102306
Pass
Phase Alignment
Done
RESET
E v al u ate CDR Lock b y
Checking Data or Using
LOS State Machine