Xilinx Virtex-5 RocketIO GTP, User Manual

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144 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 7: GTP Receiver (RX)
R
Table 7-16 defines the attributes for built-in digital oversampling.
Description
Each GTP transceiver includes a built-in 5x digital oversampling circuit, which must be
used when operating the transceiver at line rates between 100 and 500 Mb/s.
Oversampling applies to both transceivers in a GTP_DUAL tile. If oversampling is
activated for one transceiver, it is activated for both.
Configuring the GTP transceiver to use oversampling requires the following steps:
•
Configuring the 5x line rate
•
Configuring the PCS internal datapath and clocks
•
Activating and operating the oversampling block
The RocketIO GTP Wizard automatically configures the GTP_DUAL tile and makes the
oversampling ports available when generating a GTP wrapper with oversampling
enabled.
Configuring the 5x Line Rate
The SIPO in the RX PMA must provide the oversampling block with 10 bits per parallel
cycle, sampled at a rate five times faster than the desired line rate. The required line rate for
the PMA is given by
Equation 7-4 .
Equation 7-4
To achieve the required line rate, the RX divider for the transceiver must be set so that the
resulting required PLL clock rate is within the PLL operating range of 1.0 – 2.2 GHz.
Equation 7-5 shows the relationship between the required rate and the PLL clock. “Serial
In to Parallel Out (SIPO),” page 141 provides more information about the local RX divider.
Equation 7-5
The shared PLL, which is discussed in detail in “Shared PMA PLL,” page 60 , must be set to
produce the required PLL clock frequency. Equation 7-6 shows how the PLL clock
frequency is related to the frequency of CLKIN (the reference clock to the tile).
Oversampling mode automatically uses a 10-bit internal datapath in the PMA, regardless
of the INTDATAWIDTH setting. The lowest possible ratio of PLL_CLKDIV_FB to
PLL_CLKDIV_REF is recommended.
Equation 7-6
Table 7-16: RX DCDR Attributes
Attribute Description
OVERSAMPLE_MODE
This shared attribute is also defined in “Shared PMA PLL,” page
60 and “TX Buffering, Phase Alignment, and Buffer Bypass,” page
102 . It applies to both sides of both GTP transceivers on the
GTP_DUAL tile.
When TRUE, 5X oversampling is On.
PMALineRate 5 DesiredLineRate
×
=
f
PLLClock
PMALineRate PLL _ RXDIVSEL _ OUT
×
2
------------------------------------------------------------------------------------------------------------- =
f
PLLClock
f
CLKIN
5 PLL _ CLKDIV _ FB
×
PLL _ CLKDIV _ REF
-----------------------------------------------------------
×
=