Xilinx Virtex-4 ML455, User Manual

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38 www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
Chapter 4: Configuration
R
SelectMAP Interface
The SelectMAP interface is connected to the Platform Flash indirectly through the CPLD.
For the SelectMAP interface to operate correctly, the CPLD needs to be programmed (via
JTAG) such that the correct connections are made between the FPGA and the Flash.
Figure 4-5 is a general schematic for the Flash/CPLD/FPGA SelectMAP Interface.
Table 4-3 through Table 4-5 list the pinouts for the FPGA, CPLD, and Platform Flash,
respectively.
Figure 4-5: Schematic of Flash/CPLD/FPGA SelectMAP Interface
D[0:7]
REV_SEL0
REV_SEL1
CLKOUT To P2
From P2
CLKIN
U1
Platform Flash
XCF32PF
U6
CPLD
XC2C32
BUSY
CF
CE
OE/RESET
D[7:0]
CCLK M0 M1 M2
CPLD_SPARE[1:10]
FORCE
(1)
WIDE
(1)
PCIW_EN
(1)
RTR
(1)
DONE
DOUT_BUSY
RDWR_B
CS_B
PROG_B
INIT_B
31
29
33
32
5
6
34
23
28
27
U10
FPGA
XC4VLX25
39
40
12 8 2
PB_SW_h
Prog_SW_b
3 13
1
41
43
42
8
10
From/To P2
33 MHz
CPLD
CLK
DIP SW
P3
SW5
44
Flash_Image0_Select Flash_Image1_Select
MAN_A
UT
O_B
UG084_c4_05_050705
3
5
1
4
6
2
Notes:
1. FORCE, WIDE, PCIW_EN, and RTR are FPGA general-purpose I/Os.
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