Xilinx Virtex-4 ML455, User Manual

Page: 23 / 54

Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com 23
UG084 (v1.0) May 17, 2005
Voltage Regulators
R
LT1763CS88 Voltage Regulator
Figure 3-6 shows the LT1763CS8 SOIC8 linear 0.5A capable voltage regulator (U7). The
output adjust resistor is calculated from the formula given in the Linear Technology data
sheet (part number LT1763A) at
www.linear-tech.com ):
V
OUT
= 1.22V (1 + (R2/R1) + (I
ADJ
)R2)
Where I
ADJ
= 30 nA at T
J
= 25 °C, R1 < 250K
Ω
, and the output range is from 1.22V to 20V.
Choosing a 78.7
Ω
, standard 1% resistor for R1, The formula can be re-arranged to:
R2 = V
OUT
– 1.22/.01550194
Using this formula with a V
OUT
of 1.80V gives an R2 value of 37.41
Ω
. A close standard
1% resistor is 38.3
Ω
, which, when plugged back into the original formula, gives
V
OUT
= 1.8137244V (0.762% difference).
PCI 3.0V Interface Voltage Regulator
Figure 3-7 shows the LT1764AEQ (U3) voltage regulator, set at 3.0V. This regulator sources
V
CCO
to U10 LX25 Banks 6 and 10, the PCI edge connector interface banks. The following
Xilinx application notes provide PCI interface designs using Xilinx devices:
•
XAPP646 : “Connecting Virtex-II Devices to a 3.3V/5V PCI Bus”
•
XAPP653 : “3.3V PCI Design Guidelines”
•
XAPP659 : “Using 3.3V I/O Guidelines in a Virtex-II Pro Design”
Figure 3-6: LT1763CS8 Voltage Regulator
C24
3.3
µ
F
U7
LT1763CS8
R1
R2
38.3
78.7
GND
GND BYP
GND
SHDN#
IN
OUT
ADJ
1.8V 3.3V
8
5
7
6
1
2
4
3
+ C23
10
µ
F
+
UG084_c3_04_020205
Figure 3-7: LT1764AEQ (PCI 3.0V) Voltage Regulator
5V
PCI_VCC
U3
LT1764AEQ
C27
10
µ
F
+ C28
3.3
µ
F
+
2
1
3 4
5
R2
255
R1
169
GND
SHDN#
IN
OUT
ADJ
UG084_c3_06_030805
www.BDTIC.com/XILINX