Xilinx Virtex-4 ML455, User Manual

Page: 18 / 54

18 www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
Chapter 3: Hardware Description
R
Table 3-6 describes the RS232 interface pin assignments.
Table 3-7 describes the serial interface pin assignments.
Figure 3-3 is a high-level block diagram of the RS232 interface.
The RS232 DB9-F to DB9-F cable is not included in the kit. A NULL modem DB9-F to
DB9-F serial cable is required for ML455 to PC serial communications.
Table 3-6: RS232 Interface Signal Names and Pin Assignments
Signal
Name
Description
DB9M (P4)
Pin Number
MAX3316 (U5)
Pin Number
Signal Level
RX (In) Receive Data RD 2 16 Up to
±
25V
TX (Out) Transmit Data TD 3 17
±
4V
RTS (Out) Request to Send RTS 7 8
±
4V
CTS (In) Clear to Send CTS 8 9 Up to
±
25V
GND Signal Ground SG 5, 9 18 N/A
Table 3-7: Serial Interface Signal Names and Pin Assignments
Signal Name Description
MAX3316
Pin Number
(U5)
Signal Level
Direction at
MAX3316
(U5)
FPGA
Pin Number
XC4VLX25-
FF668 (U10)
T1 (In) Logic Level TX 14 0.1
×
V
CC
to 0.9
×
V
CC
Output AC12
R1 (Out) Logic Level RX 15 0.3
×
V
CC
to 0.7
×
V
CC
Input AA14
R2 (Out) Logic Level CTS 12 0.3
×
V
CC
to 0.7
×
V
CC
Input AB14
T2 (In) Logic Level RTS 13 0.1
×
V
CC
to 0.9
×
V
CC
Output AC11
Notes:
1. MAX3316 (U5) V
CC
= 2.5V.
Figure 3-3: RS232 Interface Block Diagram
TX
RX
RTS
CTS
TX
RX
RTS
CTS
T1IN
(14)
R1OUT
(15)
T2IN
(13)
R2OUT
(12)
3
2
7
8
T1OUT
(17)
R1IN
(18)
T2OUT
(8)
R2IN
(9)
DB9-M
P4
U5 U10
MAX3316
Virtex-4
FPGA
UG084_c3_02_032005
AC12
AA14
AB14
AC11
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