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Xilinx Virtex-4 LX Prototype Platform, User Manual

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Xilinx Virtex-4 LX Prototype Platform User Manual Download Page 20

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www.xilinx.com

Virtex-4 LX/SX Prototype Platform

UG078 (v1.2)  May 24, 2006

Detailed Description

R

Table 9:

Breakout Clock Pin Connections for FF1148 and FF1513

FF1148

FF1513

Label

Clock Name

Pin 

Number

Clock Name

Pin 

Number

Break

o

ut A

rea

IO_L4P_GC_LC_3

E13

IO_L4P_GC_LC_3

J21

IO_L4N_GC_VREF_LC_3

E17

IO_L4N_GC_VREF_LC_3

J20

IO_L5P_GC_LC_3

K18

IO_L5P_GC_LC_3

M21

IO_L5N_GC_LC_3

K17

IO_L5N_GC_LC_3

M20

IO_L6P_GC_LC_3

E16

IO_L6P_GC_LC_3

L20

IO_L6N_GC_LC_3

F16

IO_L6N_GC_LC_3

L19

IO_L7P_GC_LC_3

K19

IO_L7P_GC_LC_3

P22

IO_L7N_GC_LC_3

J19

IO_L7N_GC_LC_3

P21

IO_L3P_GC_LC_3

H19

IO_L3P_GC_LC_3

N22

IO_L3N_GC_LC_3

H18

IO_L3N_GC_LC_3

M22

IO_L4P_GC_LC_4

AK18

IO_L4P_GC_LC_4

AG20

IO_L4N_GC_VREF_LC_4

AK17

IO_L4N_GC_VREF_LC_4

AF20

IO_L5P_GC_LC_4

AG18

IO_L5P_GC_LC_4

AL20

IO_L5N_GC_LC_4

AG17

IO_L5N_GC_LC_4

AL19

IO_L6P_GC_LC_4

AE17

IO_L6P_GC_LC_4

AH18

IO_L6N_GC_LC_4

AE16

IO_L6N_GC_LC_4

AG18

IO_L7P_GC_VRN_LC_4

AJ19

IO_L7P_GC_VRN_LC_4

AL21

IO_L7N_GC_VRP_LC_4

AK19

IO_L7N_GC_VRP_LC_4

AK21

IO_L3P_GC_CC_LC_4

AH19

IO_L3P_GC_CC_LC_4

AJ21

IO_L3N_GC_CC_LC_4

AH18

IO_L3N_GC_CC_LC_4

AJ20

Summary of Contents for Virtex-4 LX Prototype Platform

Page 1: ...R Virtex 4 LX SX Prototype Platform User Guide UG078 v1 2 May 24 2006 P N 0402226 06 ...

Page 2: ...E TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN WHETH...

Page 3: ...1 3 Configuration Ports 12 4 JTAG Chain 13 5 JTAG Termination Jumper 13 6a Upstream System ACE Interface Connector 14 6b Downstream System ACE Interface Connector 14 6c Upstream Interface Connector 15 6d Downstream Interface Connector 16 7 Prototyping Area 16 8 VCCO Enable Supply Jumpers 16 9 VBATT 16 10 Oscillator Sockets 17 11 Differential Clock Inputs 18 12 DUT Socket 19 13 Pin Breakout 19 14 U...

Page 4: ...4 www xilinx com Virtex 4 LX SX Prototype Platform UG078 v1 2 May 24 2006 R ...

Page 5: ...m To search the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www xilinx com support Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Courier font M...

Page 6: ...on_name design_name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB 1 Name QOUT IOB 2 Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block block_name loc1 loc2 locn Convention Meaning or Use Example Convention Me...

Page 7: ...linx tools Full schematics of the board in both PDF format and ViewDraw schematic format PC board layout in Pads PCB format Gerber files in pho and pdf for the PC board There are many free or shareware Gerber file viewers available on the Web for viewing and printing these files Introduction The Virtex 4 prototype platform and demonstration boards allow designers to investigate and experiment with...

Page 8: ...lder One low voltage 14 pin DIP crystal oscillators The kit contains headers that can be soldered to the breakout area if desired These headers are useful with certain types of oscilloscope probes for either connecting function generators or wiring pins to the prototype area The Virtex 4 prototype platform the board contains a DUT FPGA and one In System Programmable Configuration PROM ISPROM The I...

Page 9: ... ACE Interface Connector LEDs UG078_01_101204 DONE LED INIT LED VBATT PROGRAM User RESET To Test Points on All Pins Configuration Port Upstream Interface Connector Downstream Interface Connector Downstream System ACE Interface Connector LVTTL 2x 2x Diff Pair Clocks SMA SMA Power Bus and Switches 5V Jack 5V Brick or VCC Jack VCCO Jack VCCAUX Jack VCCINT VCCO VCCAUX VCC3 VCC1V8 AVCC LVTTL 2x 2x Diff...

Page 10: ...he power switch enables delivery of all power to the board by way of voltage regulators situated on the backside of the board These regulators feed off a 5V external power brick or the 5V power supply jack The voltage regulators deliver fixed voltages Maximum current range for each supply will vary Table 1 page 9 shows the maximum voltage and maximum current for each onboard power supply If the cu...

Page 11: ...CO and VCCAUX 2 Power Supply Jacks One method of delivering power to the DUT is by way of the power supply jacks Consult the Xilinx data book http www xilinx com partinfo datasheet htm for the maximum voltage rating for each device you are using The power supply jacks are VCCINT Supplies voltage to the VCCINT of the DUT VCCO Supplies I O voltages to the DUT Each bank can be powered from one of two...

Page 12: ... the configuration ports and Figure 3 for setting up the JTAG chain on the board Table 2 Serial Mode Configuration Port Header Parallel Cable III IV Pins VCC3 VCC GND GND CCLK CCLK DONE D P DIN DIN PROG PROG INIT Table 3 JTAG Mode Configuration Port Header Parallel Cable IV Connector Parallel Cable III Pins Parallel Cable IV Pins VCC3V3 VCC VCC GND GND GND TMS TMS TMS TDI TDI TDI TDO TDO TDO TCK T...

Page 13: ...nother board is connected to the downstream System ACE connector or downstream interface connector jumper the DUT TDO pin to the downstream TDO pin for serial chaining The connection allows the DUT TDO pin to be connected to the next device in the chain The TCK and TMS pins are parallel feedthrough connections from the upstream System ACE interface connector to the downstream System ACE interface ...

Page 14: ...ce connector as shown in Figure 5 is used to pass configuration information to a DUT in a downstream prototype platform board from sources such as a Parallel Cable III cable or an upstream System ACE interface connector Figure 4 Upstream System ACE Interface Connector 20 Pin Female UG078_04_051004 NC UPSTREAM_TMS GND UPSTREAM_TDI GND VCC_TMP GND UPSTREAM_TCK GND UPSTREAM_TDO GND VCC3_EN VCC3_EN VC...

Page 15: ...ed by a downstream interface connector of another prototype platform board Figure 6 Upstream Interface Connector 44 Pin Female UG027_06_051004 RW_B D6 D7 DONE CCLK NC D1 D2 DIN D3 D4 D5 AFX_M0 NC NC NC CS_B AFX_M1 GND GND GND NC AFX_M2 NC GND GND GND GND GND NC NC NC NC NC PROG INIT DOUT_BUSY NC NC NC TCK TDO TDI TMS B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 A1...

Page 16: ...rough 16 each with a VCCO enable supply jumper The VCCO enable supply jumpers can connect each bank to one of the two onboard supplies VCCINT or the VCCO supply These jumpers must be installed for the Virtex 4 device to function normally 9 VBATT An onboard battery holder is connected to the VBATT pin of the DUT If an external power supply is used the associated jumper must be removed and instead u...

Page 17: ...63 FF668 Label Clock Name Pin Number Clock Name Pin Number OSC Socket Top 1 IO_L1N_GCLK_CC_LC_3 A11 IO_L1N_GCLK_CC_LC_3 B14 OSC Socket Top 2 IO_L1P_GCLK_CC_LC_3 B12 IO_L1P_GCLK_CC_LC_3 B15 OSC Socket Bottom 1 IO_L1P_GCLK_CC_LC_4 W13 IO_L1P_GCLK_CC_LC_4 AF12 OSC Socket Bottom 2 IO_L1N_GCLK_CC_LC_4 W12 IO_L1N_GCLK_CC_LC_4 AE12 Table 5 Oscillator Socket Clock Pin Connections for FF1148 and FF1513 FF1...

Page 18: ...C_3 C12 P IO_L8P_GC_LC_3 A7 IO_L8P_GC_LC_3 C13 N IO_L2N_GC_VRP_LC_3 B9 IO_L2N_GC_VRP_LC_3 A11 P IO_L2P_GC_VRN_LC_3 A10 IO_L2P_GC_VRN_LC_3 A12 N IO_L2N_GC_LC_4 W5 IO_L2N_GC_LC_4 AB10 P IO_L2P_GC_LC_4 Y5 IO_L2P_GC_LC_4 AC10 N IO_L8N_GC_CC_LC_4 W8 IO_L8N_GC_CC_LC_4 AD11 P IO_L8P_GC_CC_LC_4 W9 IO_L8P_GC_CC_LC_4 AD12 Table 7 SMA Clock Pin Connections for FF1148 and FF1513 FF1148 FF1513 Label Clock Name...

Page 19: ...Clocks in the pin breakout area that connect to the DUT clock pads are shown in Table 8 and Table 9 page 20 Table 8 Breakout Clock Pin Connections for SF363 and FF668 SF363 FF668 Label Clock Name Pin Number Clock Name Pin Number Breakout Area IO_L4P_GC_LC_3 B10 IO_L4P_GC_LC_3 B13 IO_L4N_GC_VREF_LC_3 C10 IO_L4N_GC_VREF_LC_3 B12 IO_L5P_GC_LC_3 B13 IO_L5P_GC_LC_3 A16 IO_L5N_GC_LC_3 A13 IO_L5N_GC_LC_3...

Page 20: ...3 L20 IO_L6N_GC_LC_3 F16 IO_L6N_GC_LC_3 L19 IO_L7P_GC_LC_3 K19 IO_L7P_GC_LC_3 P22 IO_L7N_GC_LC_3 J19 IO_L7N_GC_LC_3 P21 IO_L3P_GC_LC_3 H19 IO_L3P_GC_LC_3 N22 IO_L3N_GC_LC_3 H18 IO_L3N_GC_LC_3 M22 IO_L4P_GC_LC_4 AK18 IO_L4P_GC_LC_4 AG20 IO_L4N_GC_VREF_LC_4 AK17 IO_L4N_GC_VREF_LC_4 AF20 IO_L5P_GC_LC_4 AG18 IO_L5P_GC_LC_4 AL20 IO_L5N_GC_LC_4 AG17 IO_L5N_GC_LC_4 AL19 IO_L6P_GC_LC_4 AE17 IO_L6P_GC_LC_4...

Page 21: ...ser and reflect the status of pins D0 D7 and D24 D31 corresponding to LED 0 LED 15 The LED assignments are shown in Table 10 Table 10 LED Assignments and Corresponding I O Pin Number For Package Type LED After Configuration SF363 FF668 FF1148 FF1513 0 Available as user LEDs U9 AD13 G13 B16 1 V10 AC13 F13 A16 2 V11 AC15 J21 R22 3 U12 AC16 H22 T23 4 V8 AA11 H13 G15 5 V9 AA12 H14 G16 6 V12 AD14 M20 N...

Page 22: ...Flash In System Programmable Configuration PROM ISPROM is provided on the board for configuration see Table 12 Refer to Platform Flash ISPROM DS123 at http direct xilinx com bvdocs publications ds123 pdf for a detailed description Table 11 User Hardware and Corresponding I O Pins Pin Number For Package Type Label SF363 FF668 FF1148 FF1513 RESET R16 W24 AP21 AH23 Note Refer to the readme txt file f...

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